Fidel Muradali

Diagnosis in modem design - just the tip of the iceberg

When test is done right, that is to an acceptable quality specification (and without impeding productivity and cost), defective parts fail the screening process. Without splitting hairs on definition, diagnosis and debug digs deeper to determine why the part is unacceptable. Troubleshooting how and why a part (or system) fails is important. For example, this may be needed for yield improvement, process monitoring, debugging the design function, failure mode learning for R&D, or just getting a working first prototype. But the detective work can become tricky. One reason for this is that, while many segments of the product creation flow (e.g. the design and test development flows) have benefited from years of study and automation, diagnosis has somewhat lagged in the formalization of techniques. Also, the test floor equipment have been traditionally designed and operated for pass/fail oriented testing. Unless this situation improves, an effective diagnosis-friendly environment may be elusive when it is needed most.

Future ate: perspectives & requirements

Some of the claims that have concerned ATE related fields include: open architecture testers, the impact of contract manufacturing (outsourcing) o the approach to buying test time vs. testers, the impact of DFT in targeting “old” depreciated testers, the attractive cost vs. long term utilization of reduced feature or “DFT testers,” the role of niche instrumentation in future ATE form, the ability of ATE to provide value given that DFT works to curb the need for tester resources, whether or not the traditional ATE industry can continue to exist – if not, what could it look like and, of course, nobody likes paying for ATE

The impact of outsourcing on test

With outsourcing test and parts of the design, it is critical to recognize that some accustomed skills and advantages will be forced obsolete, and new ones need to be created. Fast diagnosis is an example of the latter. For some chips, outsourced IP and the host chip target the same new process. For volume ramp, it is likely that a complicated IP block will share the same yield (and even turn-on) issues as the host core. Now, however, complete details of the IP may not be known. A simple example is a netlist understood by the users gate-level diagnosis package. Cooperation with the supplier will be needed. This, however, may be cumbersome. Strong diagnosis capability is also needed for when targeting early access of a new external fabrication process. Essentially, lowered access to real fab-data can force the user to design with successively refined approximations. As artwork release may precede or coincide with process-model stability, testing of skew wafer lots may be needed to verify the design and predict yield. Should errors occur, the speed and precision of diagnosis and repair will determine the success of the early access plan.

Open Microphone - Wanted: New Test Directions & Practical Test Bottlenecks

It is time to re-align test technology R&D to target the new gaps and problems faced by industry. There is a wide range of nagging issues. For example, what is DFT for RF products? What is lowcost verification? What really are the defect mechanisms for .1um and lower? What are the new board-test issues? Will IDDQ work next year? How can manufacturing-test be optimized? The list can seem never ending.