Firdous Ahmad

Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells

Abstract Quantum-dot cellular automata is one of the most prominent nanotechnologies considered to continue scaling-down trend of sub-micron electronics. Therefore, numerous combinational and sequential circuits have been redesigned and implemented using this new technology. Considering QCA full adder cell as the basic building block in designing arithmetic circuits, great deals of attention have been paid to this research field targeting to diminish circuit latency and complexity. In this paper, contrary to conventional gate-level implementation approaches used in QCA technology, a new explicit interaction approach is utilized for designing QCA circuits. Thus, in the first step, a new well-optimized structure for three-input Exclusive-OR gate (TIEO) is proposed that is based on cell interaction. Accordingly, a low complexity and ultra-high speed QCA one-bit full-adder cell is designed employing this structure. In the next step, a comprehensive energy consumption analysis and comparison is performed over previously published QCA full-adder cells and the proposed design. QCADesigner and QCAPro tools are used for verifying circuit functioning and estimating dissipated energy.

Power analysis dataset for QCA based multiplexer circuits

Power consumption in irreversible QCA logic circuits is a vital and a major issue; however in the practical cases, this focus is mostly omitted.The complete power depletion dataset of different QCA multiplexers have been worked out in this paper. At −271.15 °C temperature, the depletion is evaluated under three separate tunneling energy levels. All the circuits are designed with QCADesigner, a broadly used simulation engine and QCAPro tool has been applied for estimating the power dissipation.

A new F-shaped XOR gate and its implementations as novel adder circuits based Quantum-dot cellular Automata (QCA)

Quantum-dot cellular automata (QCA) is a novel nanotechnology that promises smaller size, lower power consumption, with faster speed and is considered as a solution to the scaling problems in complementary metal oxide semiconductor technology. We propose a novel QCA F-shaped XOR gate. The proposed gate is simple in structure and powerful in terms of implementing digital circuits. We implement novel adder circuits like half adders and half subtractors by introducing the proposed XOR gate. The proposed adder circuits are simple in design and occupy a fraction of area, as compared to previous designs. These circuits are suitable for optimizing the complex structures. Simulation results demonstrate that the new structures have achieved significant improvements in terms of circuit complexity. The functionality of proposed structures have been checked by QCADesigner tool.

An optimal design of QCA based 2 n :1/1:2 n multiplexer/demultiplexer and its efficient digital logic realization

Abstract Quantum-Dot Cellular Automata (QCA) is a radical nanotechnology, which works at Nanoscale. In this paper, an optimal design of 2n:1 Multiplexer (MUX) and 1:2n Demultiplexer (DeMUX) is presented. A new approach has been devised to implement efficient digital logic gates using the proposed 2n:1 multiplexer. To verify the functionality of the proposed structures some Boolean proofs are performed. A detailed comparison, structural evaluation and power analysis of the proposed multiplexer with recently robust designs are analyzed. This evaluates the performance of the proposed multiplexer in terms of cell count, area clock delays and energy dissipation as compared to traditional approaches. At temperature T = 2k, the energy dissipation is evaluated under the three separate tunneling energy levels ( γ = 0.5 E k , γ = 1.0 , E k and γ = 1.5 E k ) . New implementation and simulation results of the proposed 4n:1MUX and 1:4n DeMUX are developed using the proposed 2:1 MUX and 1:2 DeMux respectively. In addition, a novel concept of QCA based Multiplexing/Demultiplexing is presented. This paves way sharing a single communication link among the number of devices at nano-regime.

Performance evaluation of efficient combinational logic design using nanomaterial electronics

Abstract Scaling down trend of CMOS transistor is approaching its lowest point, the rational substitute for the CMOS technology to attain advance improvements in terms of size, low power, and device density usage is an imperative essential. Due to the several physical limitations and circuit bounds of CMOS technology, it is the requirement of a new possible consistent model, that has small area, high device density and low power consumption. Quantum-dot Cellular Automata (QCA) is a novel approach in this direction. This paper presents a new design of 2:4 Decoder, 2:1 Multiplexer, D-Flipflop based on QCA. In addition, a nano communication circuit has been proposed which is proficient as compared to previous designs. Hamming distance approach has been used to perform the power calculations of the proposed circuits. To authenticate the functionality of the proposed designs computational simulation results has been performed using the QCAdesigner tool.

Performance evolution of 4- b bit MAC unit using hybrid GDI and transmission gate based adder and multiplier circuits in 180 and 90 nm technology

Abstract This paper presents the high-speed adder circuit design based on 18 transistor (18T) full swing gate diffusion input based logic gates and transmission based techniques to compute the sum and carry bits, respectively. The proposed adder logic operates at 1.8 and 1.2 V supply voltage. The 180 and 90 nm technology are used for the proposed architectures. The proposed design consists of less power delay products and reduces 28.57% as compared to conventional 16 transistor based adder cells. The proposed adder circuit increases the transistor count by a factor of 2. The performance of the proposed 1-bit adder circuit is testified to design 4-bit ripple carry, carry save and carry select adder circuits, with reduced circuit parameters in terms of power, delay and power delay products. In addition, the performance of the proposed adder circuit are checked to design Barun and Baugh Wooley multipliers. Finally, the low power and high-speed MAC unit is designed with the proposed adder, multiplier and register circuits. The proposed MAC unit achieves significant improvements in power-delay product as compared to conventional designs. The proposed adder, multiplier and MAC unit operation is performed wih the number of samples using Monte Carlo simulation tool. The performance evolution of the circuit parameters including power, delay and power-delay products are verified using the Cadence software Virtuoso software.

New modified-majority voter-based efficient QCA digital logic design

ABSTRACT Quantum-dot cellular automata (QCA) is an emerging nanotechnology and a possible alternative solution to the limitation of complementary metal oxide semiconductor (CMOS) technology. One of the most attractive fields in QCA is the implementation of configurable digital systems. This article presents a novel multifunctional gate called the modified-majority voter (MMV). The proposed gate works on the explicit interaction of the cell characteristic property for the implementation of digital circuits. This prominent feature of the proposed gate reduces the maximum hardware cost and implements highly efficient QCA structures. To verify the functionality of the proposed gate, some physical proofs, truth table and computational simulation results are performed. These results assured the validity of the existence of the proposed gate. It also dissipates less energy which has been calculated under three separate tunnelling energy levels using the QCAPro tool. To prove the effectiveness of the proposed MMV gate, several optimal irreversible arithmetic circuits such as three-input XOR, half-adder and full-adder are proposed. The modular layouts are verified with the freely available QCADesigner tool version 2.0.3.

A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA

Quantum-dot cellular automata, is an extremely small size and a powerless nanotechnology. It is the possible alternative to current CMOS technology. Reversible QCA logic is the most important issue at present time to reduce power losses. This paper presents a novel reversible logic gate called the F-Gate. It is simplest in design and a powerful technique to implement reversible logic. A systematic approach has been used to implement a novel single layer reversible Full-Adder, Full-Subtractor and a Full Adder–Subtractor using the F-Gate. The proposed Full Adder–Subtractor has achieved significant improvements in terms of overall circuit parameters among the most previously cost-efficient designs that exploit the inevitable nano-level issues to perform arithmetic computing. The proposed designs have been authenticated and simulated using QCADesigner tool ver. 2.0.3.