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Dive into the research topics where Florent Bouchez is active.

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Featured researches published by Florent Bouchez.


compilers, architecture, and synthesis for embedded systems | 2004

Procedure placement using temporal-ordering information: dealing with code size expansion

Christophe Guillon; Fabrice Rastello; Thierry Bidault; Florent Bouchez

In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache conflicts can be partially handled at linked time by procedure placement. Pettis and Hansen give in [1] an algorithm that reorders procedures in memory by aggregating them in a greedy fashion. The Gloy and Smith algorithm [2] greatly decreases the number of con ict-misses but increases the code size by allowing gaps between procedures. The latter contains two main stages: the cache-placement phase assigns modulo addresses to minimizes cache-conflicts; the memory-placement phase assigns final memory addresses under the modulo placement constraints, and minimizes the code size expansion. In this paper: (1) we state the NP-completeness of the cache-placement problem; (2) we provide an optimal algorithm to the memory-placement problem with complexity O(n min(n; L) log* (n)) (n is the number of procedures, L the cache size); (3) we take final program size into consideration during the cache-placement phase. Our modifications to the Gloy and Smith algorithm gives on average a code size expansion of 8% over the original program size, while the initial algorithm gave an expansion of 177%. The cache miss reduction is nearly the same as the Gloy and Smith solution with 35% cache miss reduction.


languages, compilers, and tools for embedded systems | 2007

On the complexity of spill everywhere under SSA form

Florent Bouchez; Alain Darte; Fabrice Rastello


Journal of Embedded Computing | 2005

Procedure placement using temporal-ordering information: Dealing with code size expansion

Christophe Guillon; Fabrice Rastello; Thierry Bidault; Florent Bouchez


compilers, architecture, and synthesis for embedded systems | 2008

Advanced conservative and optimistic register coalescing

Florent Bouchez; Alain Darte; Fabrice Rastello


software and compilers for embedded systems | 2010

Parallel copy motion

Florent Bouchez; Quentin Colombet; Alain Darte; Fabrice Rastello; Christophe Guillon


Archive | 2007

On the Complexity of Spill Everywhere under SSA Form Research Report n o RR2007-42

Florent Bouchez; Alain Darte; Fabrice Rastello


Archive | 2006

Register Allocation: What does Chaitin's NP-completeness Proof Really Prove?

Florent Bouchez; Alain Darte; Fabrice Rastello


Archive | 2006

New Results - Optimized Coalescing for Out-of-ssa Conversion

Florent Bouchez; Benoit Boissinot; Benoit Dupont de Dinechin; Christophe Guillon; Fabrice Rastello


Archive | 2006

Contracts and Grants with Industry - Contract with stmicroelectronics on Register Allocation and Instruction Cache Optimizations

Alain Darte; Fabrice Rastello; Florent Bouchez; Benoit Boissinot


Archive | 2006

Contracts and Grants with Industry - Minalogic SCEPTRE project with stmicroelectronics on SSA, Register Allocation, and JIT Compilation

Alain Darte; Fabrice Rastello; Florent Bouchez; Benoit Boissinot

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Alain Darte

Centre national de la recherche scientifique

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Benoit Boissinot

École normale supérieure de Lyon

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Alain Darte

Centre national de la recherche scientifique

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Quentin Colombet

École normale supérieure de Lyon

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