Florinel G. Balteanu

A 4-dB NF GPS receiver front-end with AGC and 2-b A/D

A dual-IF GPS receiver front-end integrates all the active circuitry to down-convert, amplify and digitize the 1,575.42 GHz L1 signal. The chip includes 3 dB NF LNA, 38 dB image reject mixer, VCO with integrated LC tank and varactor, PLL synthesizer, 55-dB range AGC with charge-pump control, 2-b A/D, crystal oscillator and TTL-compatible buffers. The receiver noise figure is 4 dB and maximum gain is 120 dB with a power consumption of 49 mA at 3 V supply. The AGC and 2-b A/D offer better SNR and significantly better blocking performance than the commonly used 1-b quantizers.

Polar loop transmitter for GSM/GPRS/EDGE

An EDGE transmitter using a nonlinear GSM type PA is presented. It is based on a polar loop architecture that employs separate feedback control of the amplitude and the phase of the output signal. With this approach, the problems with AM-to-PM as well as AM-to-AM of the nonlinear PA are essentially eliminated. There is no mode change between GMSK and EDGE, and the transmitter operates seamlessly in multi-slot EGPRS. The polar modulation transmitter meets all the GSM type approval requirements for both EDGE and GMSK in the quad band (850/900/1800/1900 MHz). It is part of an RF subsystem which is in production.

Analysis, simulation, and measurement of envelope tracking linearization

Additional intermodulation distortions (IMD) are generated in an envelope tracking (ET) power amplifier (PA) due to the mixing between RF input and ET signals. ET linearization can thus be achieved by the IMD cancellation. Analytical expressions depicting the ET linearization mechanism are derived. IMD cancellation is demonstrated with a three tone harmonic balance simulation. Significant linearity improvement is experimentally observed with both two-tone and modulated signals.

CMOS high bandwidth envelope tracking and power amplifiers for LTE carrier aggregation

The demand for higher data rated has lead to the utilization of both higher frequency bands, where power amplifiers (Pas) are inherently less linear, as well as carrier aggregation (CA) where linearity requirements are more stringent. In addition, cost reducing tactics for large volume applications naturally lead to CMOS based PAs which are less linear than the commonly used GaAs PAs. Envelope tracking techniques, together with digital signal processing (DSP), provide a method for achieving the linearity and efficiency required for CMOS PAs. This paper reviews the new technical challenges associated with envelope tracking methods for high data rate PAs utilized in carrier agg regation systems.

Single die broadband CMOS power amplifier and tracker with 37% overall efficiency for TDD/FDD LTE applications

This paper presents a 2.3GHz - 2.7GHz broadband CMOS FDD/TDD LTE Band 7. 38, 40 and 41 power amplifier (PA) fully integrated with a fast envelope tracker (ET) on a single 0.18μm CMOS die. The PA and the tracker achieve a 37% overall efficiency for 26.5dBm and -39dBc ACLR1. The entire design including the input/output match uses an active silicon area around 2.7mm2.