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Dive into the research topics where Fong Pong is active.

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Featured researches published by Fong Pong.


IEEE Transactions on Parallel and Distributed Systems | 1995

A new approach for the verification of cache coherence protocols

Fong Pong; Michel Dubois

We introduce a cache protocol verification technique based on a symbolic state expansion procedure. A global Finite State Machine (FSM) model characterizing the protocol behavior is built and protocol verification becomes equivalent to finding whether or not the global FSM may enter erroneous states. In order to reduce the complexity of the state expansion process, all the caches in the same state are grouped into an equivalence class and the number of caches in the class is symbolically represented by a repetition constructor. This symbolic representation is partly justified by the symmetry and homogeneity of cache-based systems. However, the key idea behind the representation is to exploit a unique property of cache coherence protocols: the fact that protocol correctness is not dependent on the exact number of cached copies. Rather, symbolic states only need to keep track of whether the caches have 0, 1, or multiple copies. The resulting symbolic state expansion process only takes a few steps and verifies the protocol for any system size. Therefore, it is more efficient and reliable than current approaches. The verification procedure is first applied to the verification of five existing protocols under the assumption of atomic protocol transitions. A simple snooping protocol on a split-transaction shared bus is also verified to illustrate the extension of our approach to protocols with nonatomic transitions. >


european conference on parallel processing | 1995

Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study

Fong Pong; Andreas Nowatzyk; Gunes Aybay; Michel Dubois

This paper presents the results for the verification of the S3.mp cache coherence protocol. The S3.mp protocol uses a distributed directory with limited number of pointers and hardware supported overflow handling that keeps processing nodes sharing a data block in a singly linked list. The complexity of the protocol is high and its validation is challenging because of the distributed algorithm used to maintain the linked lists and the non-FIFO network. We found several design errors, including an error which only appears in verification models of more than three processing nodes, which is very unlikely to be detected by intensive simulations. We believe that methods described in this paper are applicable to the verification of other linked list based protocols such as the IEEE Scalable Coherent Interface.


acm symposium on parallel algorithms and architectures | 1993

The verification of cache coherence protocols

Fong Pong; Michel Dubois

In this paper we introduce a new verification technique for cache coherence protocols at the behavior level. Protocols are specified by a Finite State Machine (FSM) model. The global state space is the Cartesian product of an arbitrary number of individual cache state spaces and is symbolically expanded. A global FSM characterizing the protocol behavior is built and protocol verification becomes equivalent to finding whether or not the global FSM may enter emoneous states. SWe expansion only takes a few steps, contrary to current approaches. The verification procedure is applied to the verification of the Illinois protocol.


international parallel and distributed processing symposium | 1993

Correctness of a directory-based cache coherence protocol: Early experience

Fong Pong; Michel Dubois

Cache coherence protocols of increasing complexities call for automated verification tools which are both efficient and reliable. Most current approaches can only verify protocols at a high level of abstraction and the model size is limited to a small number of interacting processes. By using a simple full-map directory scheme as example, we present a verification technique which is extremely efficient and is independent of the model size. Several non-obvious problems affecting the correctness of a protocol design are identified by the verification procedure.<<ETX>>


international conference on parallel processing | 1996

Formal verification of delayed consistency protocols

Fong Pong; Michel Dubois


ACM Computing Surveys | 1997

A Survey of Techniques for Verifying Cache Coherence Protocols

Fong Pong; Michel Dubois


Archive | 1997

Integrated processor/memory device with full width cache

Andreas Nowatzyk; Fong Pong; Ashley Saulsbury


Archive | 1995

Verifying distributed directorybased cache coherence protocols: s3

Fong Pong; Andreas Nowatzyk; Guiles Aybay; Michel Dubois


Archive | 1997

The Verification of Relaxed Consistency Protocols with the Sym-bolic State Model

Fong Pong; Michel Dubois


Archive | 1997

Integrierte Prozessor/Speichereinrichtung mit einem Opfer ("victim") Pufferspeicher

Andreas Nowatzyk; Fong Pong; Ashley Saulsbury

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Michel Dubois

University of Southern California

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Per Stenström

Chalmers University of Technology

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