Franc Novak

Sequential Diagnosis Tool

The Sequential Diagnosis Tool for the generation of solutions of the test sequencing problem is presented. In contrast to the conventional approach based on the symmetrical and binary tests, the advanced features of the tool are the inclusion of asymmetrical tests and tests with multiple value outcomes. The approach is illustrated by two case studies: diagnosis of boundary-scan interconnection test and system level test. The tool also represents the basis of system diagnosis software package for a system maintenance and repair.

SEU Recovery Mechanism for SRAM-Based FPGAs

The application of SRAM-based field-programmable gate arrays (FPGAs) in mission-critical systems requires error-mitigation and recovery techniques to protect them from the errors caused by high-energy radiation, also known as single event upsets (SEUs). For this, modular redundancy and runtime partial reconfiguration are commonly employed techniques. However, the reported solutions feature different tradeoffs in the area overhead and the fault latency. In this paper, we propose a low area-overhead SEU recovery mechanism and describe its application in different self-recoverable architectures, which are experimentally evaluated using a specially designed fault-emulation environment. The environment enables the user to inject faults at selected locations of the configuration memory and experimentally evaluate the reliability of the developed solutions.

Security Extension for IEEE Std 1149.1

A security extension for IEEE Std 1149.1 is proposed. It provides a locking mechanism which prevents unauthorised users to interfere via test bus with the system normal operation. The security extension requires small hardware overhead and allows full conformance with IEEE Std 1149.1.

Automated SEU fault emulation using partial FPGA reconfiguration

FPGAs are subjected to SEU faults. Fault emulation methods are used to verify the behavior of the system in the presence of fault. In this paper an automated fault emulation approach is presented. An original, fully automated extraction of SEU fault sources is introduced and the injection procedure for various types of faults in FPGA configuration and user memory is explained. Faults are injected during run-time using an embedded microprocessor. Only the resources affected by the faults are reconfigured. A prototype fault injection tool was developed and the approach is demonstrated on two different FPGA applications, micro processor BIST, and AES BIST.

Sequential Diagnosis with Asymmetrical Tests

In this paper we present the generalization of the test sequencing problem, originally defined for symmetrical tests, that also covers asymmetrical tests. We prove that the same heuristics that has been employed in the traditional solution of the problem (e.g., the AO * algorithm with heuristics based on Huffmans coding) can be employed also for the generalized case. Examples are given to illustrate the approach.

Alternative test methods using IEEE 1149.4

IEEE 1149.4 infrastructure has been aimed primarily for printed circuit board (PCB) interconnect test, parametric test of discrete components and functional test of IC cores. Methods to perform these tests have been published and experimental results using evaluation samples of IEEE 1149.4 ICs have been reported. So far, most attention has been paid to test and measurement techniques for the first two issues. Proposed methods typically employ IEEE 1149.4 infrastructure in the function of a built-in test probe that enables external test and measurement equipment to access the internal PCB points via the analog test bus. This paper describes an alternative approach based on functional transformation of the tested board by means of the existing IEEE 1149.4 resources. In this way, efficient go no-go functional test can be performed. Case studies are given to illustrate the proposed approach.

Enhancing Design-for-Test for Active Analog Filters by Using CLP(R)

We describe a computer-aided approach to automatic fault isolation in active analog filters which enhances the design-for-test (DFT) methodology proposed by Soma (1990). His primary concern was in increased controllability and observability while the fault isolation procedure was sketched only in general terms. We operationalize and extend the DFT methodology by using CLP(ℜ) to model analog circuits and by a model-based diagnosis approach to implement a diagnostic algorithm. CLP(ℜ) is a logic programming language which combines symbolic and numeric computation. The diagnostic algorithm uses different DFT test modes and results of voltage measurements for different frequencies and computes a set of suspected components. Ranking of suspected components is based on a measure of (normalized) standard deviations from predicted mean values of component parameters. The diagnosis is performed incrementally, in each step reducing the set of potential candidates for the detected fault. Case studies show encouraging results in isolation of soft faults of a given low-pass biquad filter.

A compact AES core with on-line error-detection for FPGA applications with modest hardware resources

This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity codes. The parity prediction is implemented in the AES encryption, decryption, and key expansion process. The developed solution has been upgraded to an efficient BIST with a high fault coverage and a low hardware overhead.

All-pass SC biquad reconfiguration scheme for oscillation based analog BIST

In this work, a test reconfiguration scheme for switched-capacitor stages featuring biquadratic transfer functions with finite complex zeros is presented. The proposed approach allows to perform the oscillation-based test of relevant biquad parameters without the need for complex stimulus generation or analog output processing and requires low analog area overhead. The scheme is especially suitable for implementing low-cost analog BIST of SC filter cores embedded within complex mixed-signal devices.

Oscillation Test Scheme of SC Biquad Filters Based on Internal Reconfiguration

In this paper, we explore general conditions for the oscillation based test of switched-capacitor biquad filter stages. Expressions describing the characteristics of a filter stage put into oscillation are derived and conditions for achieving oscillation by internal transformation of the filter stage are explored. Reconfiguration scheme based on the transformation of the biquad filter stage to a quadratic oscillator is studied. Theoretically the circuit can be put into oscillation by de-activating a single capacitor. Simulations, however, show that in practice a carefully designed low feed-back loop is required to achieve acceptable oscillation test mode.