Francesco Gregoretti

A Framework for Modeling, Simulation and Automatic Code Generation of Sensor Network Application

Showing functional correctness by simulation before implementation, and preserving it by automated code generation, is extremely useful to reduce the development time for an embedded application. This is even more true for wireless sensor networks, since their nodes often provide very rudimentary debugging facilities, and sufficiently large networks for realistic analysis may be expensive to deploy. While this approach, also known as model-based design, is becoming quite standard for several domains that have similar constraints as wireless sensor networks, such as automotive electronics, there is a lack of tools for this purpose in the WSN world. In order to fill this gap, in this paper we present a framework (based on Simulink, Stateflow and Embedded Coder) in which an engineer can create sensor network components (both at the application and at the protocol level) that can be used as building blocks to model, simulate and automatically generate code for different underlying platforms and operating systems.

Implementation of a UMTS turbo-decoder on a dynamically reconfigurable platform

Modern embedded systems must execute a variety of high performance real-time tasks, such as audio and image compression and decompression, channel coding and encoding, etc. Reconfigurable platforms can effectively be used in these cases, because they allow to re-use the architecture for as many applications as possible.This paper describes the implementation of a UMTS turbo-decoder on one such platform, the XiRisc reconfigurable processor. Our goal is to test the development framework and design flow that we already developed on a real industrial example. Our results shows that, with some manual effort from the designer, very good performance improvements can be achieved, using a flow close to embedded software development.

An Efficient Data Aggregation Algorithm for Cluster-based Sensor Network

Data aggregation in wireless sensor networks eliminates redundancy to improve bandwidth utilization and energyefficiency of sensor nodes. One node, called the cluster leader, collects data from surrounding nodes and then sends the summarized information to upstream nodes. In this paper, we propose an algorithm to select a cluster leader that will perform data aggregation in a partially connected sensor network. The algorithm reduces the traffic flow inside the network by adaptively selecting the shortest route for packet routing to the cluster leader. We also describe a simulation framework for functional analysis of WSN applications taking our proposed algorithm as an example.

The PAPRICA SIMD array: Critical reviews and perspectives

The PAPRICA project started in 1988 as an experimental VLSI architecture devoted to the efficient computation of data with two-dimensional structure. The main goal of the project is to develop a subsystem that could operate as an attached processing unit to a standard workstation and in perspective as a specialized processing module in dedicated systems devoted to low level image analysis, cellular neural networks emulation, DRC algorithms. The architecture has been extensively used for basic low level image analysis tasks up to optical flow computation and feature tracking, showing encouraging performance even in the first prototype version. The authors discuss the actual implementation and present a critical analysis of the project, allowing to identify some crucial points of PAPRICA design (and of array processors in general) that must be carefully considered in the case of redesign.<<ETX>>

Design and Implementation of the PAPRICA Parallel Architecture

In this paper PAPRICA, a massively parallel coprocessor devoted to the analysis of bitmapped images is presented considering first the computational model, then the architecture and its implementation, and finally the performance analysis. The main goal of the project was to develop a subsystem to be attached to a standard workstation and to operate as a specialized processing module in dedicated systems. The computational model is strongly related to the concepts of mathematical morphology, and therefore the instruction set of the processing units implements basic morphological transformations. Moreover, the specific processor virtualization mechanism allows to handle and process multiresolution data sets. The actual implementation consists of a mesh of 256 single bit processing units operating in a SIMD style and is based on a set of custom VLSI circuits. The architecture comprises specific hardware extensions that significantly improved performances in real-time applications.

Simulink-Based Codesign and Cosimulation of a Common Rail™ Injector Test Bench

This paper describes how a complete test bench for a Common Rail™ injection system has been built by means of hardware/software codesign techniques. The test bench is made up of two main components: a HW component running mainly on a FPGA device, interacting directly with the electromechanical components (namely, a high pressure pump, six electrical injectors, an electrical discharge valve, two pressure sensors), for high speed signal acquisition and generation, and for closed loop control; and a SW component, written in Visual Basic™, running on a PC, including a graphical user interface for parameters setting and system characterization. An additional signal acquisition board is also used for monitoring six load cells and for temperature control. The two components communicate through the standard PCs parallel port operated in Enhanced Parallel Port mode. The test bench is totally designed, simulated and implemented under the CodeSimulink hardware/software codesign environment, which runs as a plug-in of The Mathworks™ Simulink™ design tool. A few other commercial HW/SW codesign tools have also been considered, but none of them offered either enough performance or flexibility or, more importantly, ease of use and compatibility with existing Simulink simulation models of the various components of the test bench.

Memory interference models for a multi-microprocessor system with a shared bus and a single external common memory

Abstract The performance of a multiprocessor system with a single bus is studied by analyzing the amount of memory and bus interference. Queueing and Markov theories are used to analyze simplified models of increasing complexity and accuracy. Simulation is used to validate the analysis and to compare the obtained results with a more accurate model for which no analytical solution is found. The key result of the paper is to demonstrate that simple approximate models provide a lower bound on the system performance in the case studied. It seems therefore convenient to use such simplified models in the design and in the evaluation of multi-microprocessor systems.

3DV — An embedded, dense stereovision-based depth mapping system

This paper describes the architecture and hardware implementation of an embedded, low-cost and low-power dense stereo reconstruction system, running at 30 fps at VGA resolution. The processing pipeline includes an initial image rectification stage, a cost generation unit based on the non-parametric census transform, a state-of-the-art Semi-Global cost optimization stage, and a final minimization and noise suppression step. The hardware implementation is based on a Xilinx ZynqTM System-on-Chip, which besides the FPGA provides a physical dual-core ARM CPU, which is exploited for control and to deliver output over the integrated Gigabit Ethernet connection.

Designing low electro magnetic emissions circuits through clock skew optimization

The increased density of components within a single chip and on boards and the higher operating frequency modes available with new technologies have posed new challenges in the control of electromagnetic emissions (EME). The problem becomes even more important when considering recent regulations, which require emissions not to exceed certain values. In this paper, a new technique to reduce electromagnetic emissions of synchronous digital integrated circuits is presented. In particular, the spectrum envelope of conducted emissions is reduced significantly by properly shaping the power-supply current. For the combinational blocks, a strong reduction of conducted emissions is obtained by appropriate logic synthesis. For the sequential blocks, the reduction is obtained by spreading clock edges, in compliance with functional timing constraints. In both cases, logic synthesis and clock trees must always be tuned for the actual clock frequency. The proposed method has been applied to design a filter and strong attenuation of harmonics in the spectrum of the power supply current has been observed.

Monitoring tools for multiprocessors

Abstract Multiprocessor architectures are becoming a reality also at the commercial level and monitoring for performance is a keypoint issue due to several contention sources in a parallel environment. This paper presents the design of a monitoring structure and the architecture of a hardware instrumentation for assisting the development and monitoring of multiprocessor programs. The design is part of a larger joint research project and is actually in the implementation phase.