Francis Benistant

Novel stress-free Keep Out Zone process development for via middle TSV in 20nm planar CMOS technology

For the first time, a near-Zero Keep Out Zone TSV capability is demonstrated utilizing the Middle Of Line (MoL) layer stack process development and optimization. This is MoL layer stack consisted of a nitride, PMD oxide, and contact protection layer. Careful selection of a high CTE Contact Protection layer to compensate the TSV induced stress in Silicon (Silicon CTE is 2.3 ppm/°C) yields the near-Zero Keep Out Zone, confirmed with silicon measurement data.

Grown-in beryllium diffusion in indium gallium arsenide: An ab initio, continuum theory and kinetic Monte Carlo study

Abstract A roadblock in utilizing InGaAs for scaled-down electronic devices is its anomalous dopant diffusion behavior; specifically, existing models are not able to explain available experimental data on beryllium diffusion consistently. In this paper, we propose a more comprehensive model, taking self-interstitial migration and Be interaction with Ga and In into account. Density functional theory (DFT) calculations are first used to calculate the energy parameters and charge states of possible diffusion mechanisms. Based on the DFT results, continuum modeling and kinetic Monte Carlo simulations are then performed. The model is able to reproduce experimental Be concentration profiles. Our results suggest that the Frank-Turnbull mechanism is not likely, instead, kick-out reactions are the dominant mechanism. Due to a large reaction energy difference, the Ga interstitial and the In interstitial play different roles in the kick-out reactions, contrary to what is usually assumed. The DFT calculations also suggest that the influence of As on Be diffusion may not be negligible.

Atomistic simulation of damage accumulation and amorphization in Ge

Damage accumulation and amorphization mechanisms by means of ion implantation in Ge are studied using Kinetic Monte Carlo and Binary Collision Approximation techniques. Such mechanisms are investigated through different stages of damage accumulation taking place in the implantation process: from point defect generation and cluster formation up to full amorphization of Ge layers. We propose a damage concentration amorphization threshold for Ge of ∼1.3 × 1022 cm−3 which is independent on the implantation conditions. Recombination energy barriers depending on amorphous pocket sizes are provided. This leads to an explanation of the reported distinct behavior of the damage generated by different ions. We have also observed that the dissolution of clusters plays an important role for relatively high temperatures and fluences. The model is able to explain and predict different damage generation regimes, amount of generated damage, and extension of amorphous layers in Ge for different ions and implantation condit...

Analysis of USJ Formation with Combined RTA/Laser Annealing Conditions for 28nm High-K/Metal Gate CMOS Technology Using Advanced TCAD for Process and Device Simulation

TCAD process and device simulations are used to gain physical understanding for the integration of laser- annealed junctions into a 28 nm high-k/metal gate first process flow. Spike-RTA (Rapid Thermal Annealing) scaling used for transient enhanced diffusion (TED) suppression and shallow extension formation is investigated. In order to overcome the performance loss due to a reduced RTA, laser anneal (LSA) is introduced after Spike-RTA to form highly activated and ultra shallow junctions (USJ). In this work, the impact of different annealing conditions on the performance of NMOS and PMOS devices is investigated in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation.

Dopant–dopant interactions in beryllium doped indium gallium arsenide: An ab initio study

We present an ab initio study of dopant-dopant interactions in beryllium-doped InGaAs. We consider defect formation energies of various interstitial and substitutional defects and their combinations. We find that all substitutional-substitutional interactions can be neglected. On the other hand, interactions involving an interstitial defect are significant. Specially, interstitial Be is stabilized by about 0.9/1.0 eV in the presence of one/two BeGa substitutionals. Ga interstitial is also substantially stabilized by Be interstitials. Two Be interstitials can form a metastable Be-Be-Ga complex with a dissociation energy of 0.26 eV/Be. Therefore, interstitial defects and defect-defect interactions should be considered in accurate models of Be doped InGaAs. We suggest that In and Ga should be treated as separate atoms and not lumped into a single effective group III element, as has been done before. We identified dopant-centred states which indicate the presence of other charge states at finite temperatures, specifically, the presence of Beint+1 (as opposed to Beint+2 at 0K).

Contact model based on TCAD-experimental interactive algorithm

This work demonstrated a novel method utilizing Sentaurus Technology Computer Aided Design simulation along with experiments to intermediately extract Schottky barrier height and contact resistance in FinFETs. The proposed algorithm can automatically calibrate contact model based on measurement data. This interactive contact model is also capable of prediction of contact resistance sensitivity including key process features such as implant energy, dose and thermal process based on a design of experiment splits. This robust, physical and efficient contact model provides insightful understandings of the metal-semiconductor contact in FinFETs. It can be easily implemented in simulation tools for device design in state-of-art semiconductor technology development.

Advanced TCAD simulation of local mismatch in 14nm CMOS technology FinFETs

Local statistical variability (mismatch) is very important in advanced CMOS technologies critically affecting, among others, SRAM supply and holding voltages, performance and yield. TCAD simulation of statistical variability is essential for identification of variability sources and their control in the technology development and optimization. It also plays an important role in the development of accurate statistical compact models for SRAM design, statistical standard cell characterization and statistical circuit simulation and verification. In this paper we compare the TCAD simulation results of statistical variability in 14nm CMOS FinFET technology with Silicon measurements in order to understand the relative role of key statistical variability sources, to assist the technology optimization and to generate target characteristics for statistical compact model extraction.

Influence of stress induced CT local layout effect (LLE) on 14nm FinFET

In this paper, we present a new local layout effect in 14nm FinFET due to different CT layout designs (CT extension, CT spacing, and PC past RX distance). Based on 14nm FinFET experimental data, the CT LLE effect induces up to 50mV Vtsat shift, and ∼20% current change. NFET performance is enhanced by ∼7%, while the PFET performance shows slight degradation. Based on TCAD simulation, the CT LLE is fully analyzed and explained by the tensile stress induced in the inter-layer dielectric (ILD).

Versatile technology modeling for 22FDX platform development

The 22FDX platform offered by GLOBALFOUNDRIES consists of a family of differentiated products architected to enable applications across a variety of market segments such as RF & Analog, Ultra-low Power (ULP), and Ultra-low Leakage (ULL). In order to ensure the successful development of these new products, as well as to meet the time-to-market constraints, predictive Technology Computer Aided Design (TCAD) tools have been extensively used to guide development efforts, narrow the experimental conditions and reduce the number of learning cycles. The areas of impact expanded to not only predicting device outcome from process input, but also to topics traditionally not addressed by TCAD. In this paper, we present a comprehensive TCAD that has been deployed to optimize core oxide transistors, define approaches to attain ULL targets, and simultaneously investigate the AC behavior at lower operating voltages while improving RF performance. The all-encompassing co-optimization of process, device and layout has been achieved within the same platform.

TCAD analysis of SiGe channel FinFET devices

SiGe FinFET devices have many unique device elements which differ from conventional Si FinFET devices. Here we discuss their threshold voltage sensitivity, stress profiles, long channel mobility behavior, and the presence of traps at the gate oxide interface. In order to achieve a well-performing SiGe FinFET device it is important to understand the physical nature of these elements and incorporate them in a well-calibrated TCAD deck. In this paper, we examine each element with experimental data and calibrate the TCAD deck by introducing new boundary conditions, implementing a new Dit extraction method, and adjusting the material parameters. Special consideration is given to the treatment of interface traps since the readout of the trap density with the conductance method used in experiments does not represent the actual trap distribution. Finally, we review the short channel transistor performance and provide guidelines on how to achieve a high-performing device.