Francisco Messina

A Novel Modular Positive-Sequence Synchrophasor Estimation Algorithm for PMUs

A novel modular positive-sequence estimation algorithm for phasor measurement units (PMUs) is described in this paper with a focus on the restrictions imposed by the IEEE C37.118.1–2011 standard. The first stage consists in a three-phase demodulator which allows us to separate the positive-sequence from the negative-sequence signal in the frequency domain and to eliminate the zero-sequence signal. The second stage is a prefilter that mitigates noise and interference, thus relaxing the filtering requirements of the following stage. The suitability of a linear-phase FIR filter is shown and a comparison of single and multistage designs is presented. On the third stage, a digital state-space-based extension of a synchronous reference frame-phase-locked loop is used for tracking of amplitude, phase, frequency, and rate of change of frequency. It is shown that a phase predictor inside the loop is required. The fourth stage is a compensation algorithm which takes into account the narrowband nature of the input signal to perform an accurate compensation of the filter effects on the signal of interest. Analytical properties of the system are then presented, providing insight into the main factors that affect global performance. Finally, a strict evaluation of the system is presented for both M and P class PMU.

Design of synchrophasor estimation systems with convex semi-infinite programming

In this paper, we present a design methodology for synchrophasor estimation systems based on a convex semi-infinite optimization approach. Concretely, we present a suitable objective function for the problem and show how different performance constraints can be formulated. The advantage of this over most methods is that it allows us to control precisely and completely the behavior of the system on both frequency and time domains. Thus, it gives an optimal and extremely flexible tool for a designer who wishes to obtain a particular desired performance. In particular, we show the advantages of this methodology by comparing it with standard designs on a study case on the basis of the IEEE Std. C37.118.1-2011.

An accurate phase compensation algorithm for PMUs

This paper describes an algorithm for accurate filter phase compensation in PMUs. It is based on two realistic assumptions: (1) the group delay of the filtering stages in the system is approximately constant in the frequency range of interest and (2) the information input signal is narrowband. Numerical results confirm the accuracy improvement of this algorithm with respect to a standard compensation and compliance with the IEEE Std. for synchrophasor measurements.

A single-phase dynamic phasor estimation system: Analysis of performance and computational cost

This paper presents a new single-phase technique for dynamic phasor estimation using a sample by sample digital processing approach. The estimation process is performed in three stages. In the first stage, an efficient FIR filtering of the input signal is made to reject out-of-band and harmonic interference. The second stage uses a parameterized EPLL to track amplitude, phase, frequency and ROCOF. The final stage compensates the delay and any possible phase and amplitude distortion. The proposed design is compared against a well known window DFT method known as IpD2FT, which requires a large buffer and iterative process for each report. The goal is to develop a PMU system compliant with the IEEE Std. C37.118.1a and compare both algorithms in terms of performance and computational cost.