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Design of a high complexity superscalar microprocessor with the portable IDPS ASIC library

This paper presents the design flow for a superscalar VLIW microprocessor using the 0.8 /spl mu/ CMOS portable ASIC library developed in the framework of the ESPRIT2 IDPS project. A full set of cell libraries and macro-block generators have been used, in order to achieve fast design cycle and to maintain a high level of integration and performance. The final circuit contains about 875000 transistors with a die size of 14.6/spl times/14.6 mm/sup 2/. The chip design and verification have been performed with new advanced CAD tools developed in the IDPS project. The layout uses a symbolic approach in order to provide process independence. The package is a 428-pin PGA.<<ETX>>

An out-of-order superscalar processor on FPGA: the ReOrder buffer design

Embedded systems based on FPGA (Field-Programmable Gate Arrays) must exhibit more performance for new applications. However, no high-performance superscalar soft processor is available on the FPGA, because the superscalar architecture is not suitable for FPGAs. High-performance superscalar processors execute instructions out-of-order and it is necessary to re-order instructions after execution. This task is performed by the ROB (ReOrder Buffer) that uses usually multi-ports RAM, but only two-port buffers are available in FPGA. In this work, we propose a FPGA friendly ROB (ReOrder Buffer) architecture using only 2 ports RAM called a multi-bank ROB architecture. The ROB is the main and more complex structure in an out-of-order superscalar processor. Depending on processor architecture parameters, the FPGA implementation of our ROB compared to a classic architecture, requires 5 to 7 times less registers, 1.5 to 8.3 times less logic gates and 2.6 to 32 times less RAM blocks.

RWT: Suppressing Write-Through Cost When Coherence is Not Needed

In shared-memory multicore architectures, handling a write cache operation is more complicated than in single processor systems. A cache line may be present in more than one private L1 cache. Any cache willing to write this line must inform all the other sharers. Therefore, it is necessary to implement a cache coherence protocol for multicore architectures. At present, directory based protocols are popular cache coherence protocols in both industry and academic domains because of their reduced coherence traffic compared to snooping protocols, at the expense of an indirection. The write policy - write through or write back - is crucial in the protocol design. The write-through policy reduces the bandwidth because it augments the write traffic in the interconnection network, and also augments the energy consumption. However, it can efficiently solve the false sharing problem via write updates. In this paper, we introduce a new way to reduce the write traffic of a write-through coherence protocol by combining write-through coherence with a write-back policy for non coherent lines. The baseline write-through used as reference is a scalable hybrid invalidate/update protocol. Simulation results show that with our enhanced protocol, we can reduce at least by 50% the write traffic in the interconnection network, and gain up to 20% performance compared with the baseline write-through protocol.

Morpheo: A high-performance processor generator for a FPGA implementation

Complex applications, such as multimedia, telephony or cryptography, in embedded systems must provide more and more performance that can be achieved by using multiple levels of parallelism. Today, FPGA are viable alternatives for these kinds of applications. Unfortunately, the available processors on FPGA do not provide sufficient performance. This work proposes the Morpheo tool that is a generator of configurable high performance processors dedicated to FPGA. As the FPGA architecture is more restrictive than on ASIC, VHDL models produced by Morpheo can also be used for an ASIC implementation. The main advantage is that there is no need for specific components, therefore, processors are easier to generate. Despite the architectural changes related to the FPGA target, the IPC (Instructions Per Cycle) of 2-way and 4-way superscalar processors are, respectively, 0.81 and 0.74 times that of M5 processors (ASIC targeted) with corresponding parameters. These processors can be placed in a Xilinx Virtex-5 xc5vlx330 using 15% and 31% of hardware available resources and perform at, respectively, 79 MHz and 72 MHz.

Smart security management in secure devices

Among other threats, secure components are subjected to physical attacks whose aim is to recover the secret information they store. Most of the work carried out to protect these components generally consists in developing protections (or countermeasures) taken one by one. But this “countermeasure-centered” approach drastically decreases the performance of the chip in terms of power, speed and availability. In order to overcome this limitation, we propose a complementary approach: smart dynamic management of the whole set of countermeasures embedded in the component. Three main specifications for such management are required in a real-world application (for example, a conditional access system for pay-TV): it has to provide capabilities for the chip to distinguish between attacks and normal use cases (without the help of a human being and in a robust but versatile way); it also has to be based on mechanisms which dynamically find a trade-off between security and performance; all these mechanisms have to be formalized in a way that is clearly understandable by the designer. In this article, a prototype implementing such a security management system is described. The solution is based on a double-processor architecture: One processor embeds a representative set of countermeasures (and mechanisms to define their parameters) and executes the application code. The second processor, on the same chip, applies a given security strategy, but without requesting sensitive data from the first processor. The chosen strategy is based on fuzzy logic reasoning to enable the designer to describe, using a fairly simple formalism, both the attack paths and the normal use cases. A proof of concept has been proposed for the smart card part of a conditional access for pay-TV, but it could be easily fine-tuned for other applications.

GECOS : Mécanisme de synchronisation passant à l’échelle à plusieurs lecteurs et un écrivain pour structures chaînées

Ce papier presente GECOS (GEneration Counter Optimistic Synchronisation), un nouveau mecanisme de synchronisation permettant un acces lock-free (sans verrou) aux structures chainees a plusieurs lecteurs et un ecrivain. Ce mecanisme a ete specialement concu pour prendre en consideration les contraintes des architectures manycore en permettant non seulement des performances qui passent a l’echelle, mais aussi une utilisation optimale de la memoire. Les premiers resultats, obtenus sur un systeme a 64 cœurs, montrent de tres bonnes performances lors du passage a l’echelle, qui sont comparables, voire superieures, a celles des mecanismes les plus performants tels que le mecanisme Read-Copy-Update ou le mecanisme Hazard Pointers.