Frank Sill Torres

USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA

Quantum-dot cellular automata (QCA) is an emerging technology, conceived in face of nanoscale limitations of CMOS circuits, with exceptional integration density, impressive switching frequency, and remarkable low-power characteristics. Several of the current challenges toward the progress of QCA technology is related to the automation of the design process and integration into existing design flows. In this regard, this paper proposes the universal, scalable, efficient (USE), and easily manufacturable clocking scheme. It solves one of the most limiting factors of existing clock schemes, the implementation of feedback paths and easy routing of QCA-based circuits. Consequently, USE facilitates considerably the development of standard cell libraries and design tools for this technology, besides avoiding thermodynamics problems. Case studies presented in this paper reveal an area reduction of up to factor 5 and delay decrease by up to factor 3 in comparison with an existing advanced clocking scheme.

Robust modular Bulk Built-in Current Sensors for detection of transient faults

Soft error resilience is an increasingly important requirement of integrated circuits realized in CMOS nanometer technologies. Among the several approaches, Bulk Built-in Current Sensors (BBICS) offer a promising solution as they are able to detect particle strikes immediately after its occurrence. Based on this idea we demonstrate a novel modular BBICS (mBBICS) that tackles the main problems of these integrated sensors - area, leakage, and robustness. Simulations based on a predictive nanometer technology indicate competitive response times for high performance applications at the cost of 25% area overhead and very low power penalty. Thereby, all simulated particle strikes that lead to transient faults could be detected. Additionally reliability analysis proved the robustness of the proposed mBBICS against wide variations of temperature and process parameters.

Comparison of bulk built-in current sensors in terms of transient-fault detection sensitivity

Several architectures of Bulk Built-In Current Sensors (BBICS) were recently proposed to monitor transient faults induced on integrated circuits by radiation or malicious sources. This work compares for the first time all existing static BBICS architectures in terms of their sensitivities to detect transient faults. In addition, we propose a new static BBICS that presents better results of transient-fault detection sensitivity than previous sensor architectures.

Evaluation of the full operational cycle of a CMOS transfer-gated photodiode active pixel

In this paper we evaluate the full operational cycle of the active-pixel circuit for CMOS image sensors in which four field-effect transistors are suitably combined with an ordinary photodiode; meaning a vertical p-n junction, as opposed to photogates, and with no custom pinned layer. Although this circuit topology itself is not novel, this evaluation intends to shine new light on the use of regular photodiodes. They became largely in disuse in four-transistor image chips under earlier process and design circumstances because the fourth transfer-gate FET did not hold a constant signal long enough and not for a fixed time. Our aim is to investigate the full underlying operational regimen of the transfer gate to propose that a regular photodiode might again be a choice to consider in the four-transistor pixel configuration, not only in conventional imaging but also in dedicated optical applications. The use of an ordinary p-n junction photodiode is advantageous as it offers full compatibility with even elementary mainstream CMOS processes. This investigation resorts to experiments and models both with fabricated integrated pixels and with a macro-pixel circuit implementation.

Exploration of noise robustness and sensitivity of bulk current sensors for soft error detection

Radiation induced soft errors are a serious concern not only for memories but also logic circuits. Amongst the several proposed countermeasures, Bulk Built-in Current Sensors represent a promising approach with fast response times and reasonable costs in terms of area and power. However, these circuits, as well as similar sensors that measure substrate effects, are strongly susceptible to substrate noise. The intention of this work is a thorough analysis of activation mechanism and noise behavior of these sensors as well the exploration of strategies to increase noise robustness.

Efficient and scalable cross-by-pass-mesh topology for networks-on-chip

This study presents an efficient and scalable networks-on-chip (NoC) topology termed as cross-by-pass-mesh (CBP-Mesh). The proposed architecture is derived from the traditional mesh topology by addition of cross-by-pass links in the network. The design and impact of adding cross-by-pass links on the topology is analysed in detail with the help of synthetic, hotspot as well as embedded traffic traces. The advantages of proposed CBP-Mesh as compared with its competitor topologies include reduction in the network diameter, increase in bisection bandwidth, reduction in average numbers of hops, improvement in symmetry and regularity of the network. The synthetic traffic traces and some real embedded system workloads are applied on the proposed CBP-Mesh and its competitor two-dimensional-based NoC topologies. The comparison of analytical results in terms of performance and costs for different network dimensions indicate that the proposed CBP-Mesh offers short latency, high throughput and good scalability at small increase in power and energy.

Automatic layout integration of bulk built-in current sensors for detection of soft errors

Soft error resilience is of rising importance for the design of integrated circuits realized in CMOS nanometer technologies. Therefore, Bulk Built-In Current Sensors (BBICS) have been proposed as a fast and efficient technique for detecting transient faults that might lead to soft errors. An important requirement for application of these sensors in common designs is the automatic integration. The aim of this work is to present a methodology for automatic insertion of BBICS in common standard cell designs. Further, two different placement strategies are introduced and compared. Experiments demonstrate the feasibility of the approach and indicate requirements for future BBICS developments in order to reduce area offset.

Comparative analysis of network-on-chip simulation tools

Network-on-chip (NoC) is a reliable and scalable communication paradigm deemed as an alternative to classic bus systems in modern systems-on-chip designs. Consequently, one can observe extensive multidimensional research related to the design and implementation of NoC-based systems. A basic requirement for most of these activities is the availability of NoC simulators that enable the study and comparison of different technologies. This study targets the analysis of different NoC simulators and highlights its contributions towards NoC research. Various NoC tools such as NoCTweak, Noxim, Nirgam, Nostrum, BookSim, WormSim, NOCMAP and ORION are evaluated and their strengths and weaknesses are highlighted. The comparative analysis includes methods for estimation of latency, throughput and energy consumption. Further, the exemplary real world application, video object plane decoder is mapped on a 2D mesh NoC using different mapping algorithms under NOCMAP and NoCTweak simulators for comparative analysis of the NoC simulators and their embedded mapping algorithms.

A Methodology for Standard Cell Design for QCA

QCA (Quantum-Dot Cellular Automata) is an emerging nanotechnology that has the potential to replace current CMOS technologies. QCA permits extremely low power consumption, since its working principle is not based on electric current flow but on Coulomb interaction. The development of Electronic Design Automation (EDA) tools and flows is an essential step towards the applicability of QCA for integrated designs. However, the scarce number of works in this field highlights that there is plenty of room for the development of new EDA methodologies for emerging nanotechnologies. Standard cells play an important role in this context, since the development of routing and placement algorithms are strongly related to their existence. This work presents a methodology for standard cell design for QCA as well as the exemplary QCA cell library ONE, which is based on the recently proposed USE (Universal, Scalar and Efficient) clocking scheme. Two representative case studies indicate the feasibility of the approach.

Noise analysis of integrated bulk current sensors for detection of radiation induced soft errors

Current CMOS technologies show an increasing susceptibility to a rising amount of failure sources. This includes also radiation induced soft errors, which requires countermeasures on several design levels. Hereby, Bulk Built-In Current Sensors represent a promising approach on circuit level. However, it is expected that these circuits, like similar sensors measuring substrate effects, are strongly susceptible to substrate noise. The intention of this work is an in-depth noise analysis of representative bulk sensor based on extracted layout data. Thereby, several aspects are considered, like sensor activation thresholds, impact of the distance to the noise source, and noise generation by a test circuits. Results indicate that already rms values of 5 to 10 % of the supply voltage can lead to false detections and that these values are in the same order of magnitude as the noise generated by test circuits.