Frans de Jong

Boundary scan test, test methodology, and fault modeling

The test technique called “boundary scan test” (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.

Static component interconnect test technology (SCITT) a new technology for assembly testing

Modern packaging technology combined with densely populated assemblies requires efficient design for test features. In particular, modern memories with complex interfaces need to be addressed. This paper presents the details of a test technology that makes assembly test more efficient. The method is based on the implementation of XOR and XNOR gates to bypass a functional circuit. It is compatible yet complimentary to boundary-scan. Mathematical proof and simulation results show the effectiveness of this method for detection and diagnosis of assembly faults. Known alternatives are compared for test coverage.

BST Design Languages

This chapter describes various software tools developed to support automation in Boundary-Scan testing. These tools support the features of Boundary-Scan applications in various phases of the product life cycle, where ‘product’ may be defined as IC, PCB or system. Table 4-1 intends to place the various tools in their right context, which may be useful when reading this chapter. Table 4-1 General and BST Software Support Tools Documentation/Description Design Design Verification Test Preparation IC BSDL (VHDL) Automatic BSC inserter (TIM/BSR compiler) Conformance with Logic Analyzer ATPG for inserted BS Logic PCB EDIF -- Disassembly BS Test Pattern Gen. System -- -- Disassembly BS Test Pattern Gen.

The Boundary-Scan Test Standard

This chapter describes the elements defined by the IEEE Std 1149.1 for the Standard Test Access Port and Boundary-Scan Architecture. First the constituent parts of the Boundary-Scan architecture (both the mandatory and the optional items), are described followed by the instructions. The final section gives some rules which should be followed when BST designs are to be documented. Numerous descriptions are clarified, each with a practical example, making this chapter a tutorial for BST. For more detailed specifications of the BST standard please refer to the listing in the Appendix of this book, where these specifications are summarized for those readers who do not have the official IEEE Std 1149.1 manual readily available.

PCB Test Strategy Backgrounds

This chapter describes the basics behind the PCB test procedures. First the infrastructure of BST net itself is considered, which should be tested on its integrity before any other test is performed. Next the possible faults during the PCB manufacturing phase are described, followed by a discussion of various test pattern sequences and diagnostic algorithms required to perform board interconnect tests. Cluster testing is treated as a separate item in a following section. By searching the minimum test vector set for memory interconnect tests, it is proven that BST is an excellent tool for these type of tests as well. In the last section an architecture of a Boundary-Scan test flow is given.

Hardware Test Innovations

This chapter describes provisions that can be made in order to support Boundary-Scan testing for printed circuit boards (PCBs) and a system. A number of on-chip provisions are also illustrated.