Frans Dijkhuizen

Modular Multilevel Converters for HVDC Applications: Review on Converter Cells and Functionalities

In this paper, the principle of modularity is used to derive the different multilevel voltage and current source converter topologies. The paper is primarily focused on high-power applications and specifically on high-voltage dc systems. The derived converter cells are treated as building blocks and are contributing to the modularity of the system. By combining the different building blocks, i.e., the converter cells, a variety of voltage and current source modular multilevel converter topologies are derived and thoroughly discussed. Furthermore, by applying the modularity principle at the system level, various types of high-power converters are introduced. The modularity of the multilevel converters is studied in depth, and the challenges as well as the opportunities for high-power applications are illustrated.

Five level cross connected cell for cascaded converters

Proposed here is an alternate Five-level four-quadrant cascaded multilevel converter cell configuration that compared to the other cell configurations, for dc fault current limitation, will be more compact and avoid the external dc breaker. Loss comparison on cells with dc fault blocking capability for the cascaded converter is also presented.

Current source modular multilevel converter for HVDC and FACTS

A current source modular multilevel converter (MMC) is proposed for high voltage AC/DC power conversion applications, such as HVDC and FACTS. Current source converters possess the advantage of short-circuit fault tolerance, which is a pivotal feature for grid applications. By partially following the circuit duality transformations, the proposed converter is derived from the well-known voltage source MMC. Inductor-based current source cells are connected in parallel and form a current source arm that can synthesize a desired current waveform. By adding a reduced-energy capacitor in parallel to each current source arm, these arms can be further connected in series, thereby allowing voltage scaling. By using fully controllable switches, the converter is capable of providing full control on its active and reactive power. Protection schemes against open-circuit failures inside the inductor cells are also proposed. Simulation results show the operation of the current source MMC and its capability of DC fault tolerance.

Fault Tolerant Operation of Power Converter with Cascaded Cells

Multilevel converters based on cascaded cells are well suited for high power applications, due to good control performance, extensive modularity and excellent harmonic distortion. A vital requirement in high power converters is being fault-tolerant, so that a single fault in a cell does not lead to the trip of the entire converter. This paper presents a strategy for fault-tolerance on cell level with Integrated Gate Commutated Thyristors (IGCT). The concept is based on initiating a surge in a phase leg in a failing cell, limited by a di/dt reactor leading to a short circuit failure mode of the IGCT thereby excluding the cell from the chain.

Analysis of modular multilevel converters with DC short circuit fault blocking capability in bipolar HVDC transmission systems

This paper analyzes the station-internal phase-to-ground fault in bipolar HVDC transmission systems. An overvoltage problem due to the existence of the bipolar cells in the modular multilevel converter (MMC) arms closer to the grounding pole are presented. Consequently, a new hybrid arm MMC is proposed to overcome the overvoltage problem while providing the benefits of: a lower number of cells, fewer switching devices and lower conduction losses. Guidelines are developed and confirmed by simulation results to determine the required number of cells to block the DC side fault.

A Review of Hybrid Topologies Combining Line-Commutated and Cascaded Full-Bridge Converters

This paper presents a review of concepts for enabling the operation of a line-commutated converter (LCC) at leading power angles. These concepts rely on voltage or current injection at the ac or dc sides of the LCC, which can be achieved in different ways. We focus on the voltage and current injection by full-bridge (FB) arms, which can be connected either at the ac or dc sides of the LCC and can generate voltages that approximate ideal sinusoids. Hybrid configurations of an LCC connected at the ac side in series or in parallel with FB arms are presented. Moreover, a hybrid configuration of an LCC connected in parallel at the ac side and in series at the dc side with an FB modular multilevel converter is outlined. The main contribution of this paper is an analysis and comparison of the mentioned hybrid configurations in terms of the capability to independently control the active (P) and reactive power (Q).

Hybrid topologies for series and shunt compensation of the line-commutated converter

This paper presents two concepts for enabling the operation of a line-commutated converter (LCC) at leading power angles. The concepts are based on voltage or current injection at the ac side of an LCC, which can be achieved in different ways. However, this paper focuses on the voltage and current injection by series-connected full-bridge cells that can generate voltages that approximate ideal sinusoids. Thus, hybrid configurations of an LCC connected at the ac side in series or in parallel with full-bridge cells are presented. Finally, these hybrid configurations are compared in terms of voltage and current rating.

Investigation of the surge current capability of the body diode of SiC MOSFETs for HVDC applications

The surge current capability of the body-diode of SiC MOSFETs is experimentally analyzed in order to investigate the possibility of using SiC MOSFETs for HVDC applications. SiC MOSFET discrete devices and modules have been tested with surge currents up to 10 times the rated current and for durations up to 2 ms. Although the presence of stacking faults cannot be excluded, the experiments reveal that the failure may occur due to the latch-up of the parasitic n-p-n transistor located in the SiC MOSFET.