Frederic Reblewski

Serial fault emulation

A hardware emulator based approach has been developed to perform test evaluation on large sequential circuits (at least tens of thousands of gates). This approach relies both on the flexibility and on the reconfigurability of hardware emulators based on dedicated reprogrammable circuits. A Serial Fault Emulation (SFE) method in which each faulty circuit is emulated separately has been applied to gate level circuits for Single Stuck Faults (SSFs). This approach has been implemented on the Meta Systemss hardware emulator which is capable of emulating circuits of 1,000,000 gates at rates varying from 500 kHz to several MHz. Experimental results are provided to demonstrate the efficiency of SFE. They indicate that SFE should be two orders of magnitude faster than sofware approaches for designs containing more than 100000 gates.