Fuat Karakaya

Neural identification of dynamic systems on FPGA with improved PSO learning

This work introduces hardware implementation of artificial neural networks (ANNs) with learning ability on field programmable gate array (FPGA) for dynamic system identification. The learning phase is accomplished by using the improved particle swarm optimization (PSO). The improved PSO is obtained by modifying the velocity update function. Adding an extra term to the velocity update function reduced the possibility of stucking in a local minimum. The results indicates that ANN, trained using improved PSO algorithm, converges faster and produces more accurate results with a little extra hardware utilization cost.

FPGA implementation of neuro-fuzzy system with improved PSO learning

This paper presents the first hardware implementation of neuro-fuzzy system (NFS) with its metaheuristic learning ability on field programmable gate array (FPGA). Metaheuristic learning of NFS for all of its parameters is accomplished by using the improved particle swarm optimization (iPSO). As a second novelty, a new functional approach, which does not require any memory and multiplier usage, is proposed for the Gaussian membership functions of NFS. NFS and its learning using iPSO are implemented on Xilinx Virtex5 xc5vlx110-3ff1153 and efficiency of the proposed implementation tested on two dynamic system identification problems and licence plate detection problem as a practical application. Results indicate that proposed NFS implementation and membership function approximation is as effective as the other approaches available in the literature but requires less hardware resources.

Implementation of HOG algorithm for real time object recognition applications on FPGA based embedded system

Recent years HOG algorithm has been used to recognize objects in images, with complex content, with a very high success rate. Hardware implementation of this algorithm is very important because of the fact that it can be used in many object recognition applications. In this work HOG algorithm is implemented on FPGA to recognize different geometrical figures with a very high success rate. Objects vertical and horizontal edges have been sharpened using edge detection algorithms to calculate magnitude and angle of the local gradients. Obtained result are used to construct the histograms of gradient orientation. It is observed that each constructed histogram have distinctive features for every object. Rule based classifiers has been used to implement a successful real time object recognition approach on embedded system.

Hardware implementation of Discrete Wavelet Transform and Inverse Discrete Wavelet Transform on FPGA

In this paper, hardware implementation of the Discrete Wavelet Transform (DWT) and Inverse Discrete Wavelet Transform (IDWT) based on FPGA is explained. DWT and IDWT algorithms are implemented on the Altera Cyclone-II FPGA. Filtering processes of rows and columns are seriatim applied as in level-by-level architecture. But both addressing for read/write and DWT/IDWT processes are implemented via only one filter by checking kind of filter to be applied. This usage has got advantages of both elapsed times for read/write processes and cost of hardware area. Implementation DWT and IDWT on the hardware is required only 2% hardware area with this approximation.

The effect of genetic algorithm parameters on the solution of plate location detection

In this study, a new method based on genetic algorithm and neural networks for determining licence plate location is proposed. The effect of genetic algorithm parameters on the quality of solutions is investigated. The method is able to successfully locate a licence plate in avearge 40 msn, on the image of 768x288 size. This score is 200 times quicker compared to sequential search method. Futhermore the method is able to find multiple plates in an image.

Implementation of edge dependent interpolation based de-interlacer on FPGA

Interlacing technique aims to lower the costs of high definition video systems by reducing the data amount sent to receiver unit. Regeneration of image at the receiver unit is an important point of interlacing method. In this study, regeneration (de-interlacing) of frames that are sent to receiver unit is implemented by using edge dependent interpolation method. The method is implemented using VHDL on Altera Cyclone-II FPGA. The method avoids reading of redundant data which yields to reduced operation time. Implementation occupies only %3 of the FPGA that is used in this study.

SIH: segmented intensity histogram for orientation estimation in image matching

In this paper, we propose a fast and effective new method to reduce the overhead cost of orientation estimation. The proposed method uses the summation of intensity values from segments of image patches and forms a histogram based on those values. As a result, it is faster than SIFT-like algorithms because it does not require computation of gradient orientations and magnitudes. Also, it is as fast as other intensity-based algorithms with better image matching performance. Proposed method could be easily integrated to any image matching algorithms. Test results indicate that SIFT integrated with proposed orientation estimation method produces comparable results as the original multi-angle SIFT algorithm with less execution time.