Fujiang Lin

Trapping of surface plasmon wave through gradient corrugated strip with underlayer ground and manipulating its propagation

Corrugated metal surface with underlayer metal as ground is designed as spoof surface plasmons polaritons (SSPPs) structure in microwave frequencies. Efficient conversion from guided wave to SSPP is required for energy feeding into and signal extracting from such plasmonic structure. In this paper, first a high efficient transition design is presented by using gradient corrugated strip with underlayer metal as ground and by using the impedance matching theory. The SSPP wave is highly confined within the teeth part of the corrugated surface. By using this characteristic, then the simple wire-based metamaterial is added below the strip to manipulate the SSPP wave within the propagating band. Two aforementioned devices are designed and fabricated. The simulated and measured results on the scattering coefficients demonstrate the excellent conversion and excellent manipulating of SSPP transmitting. Such results have very important value to develop advanced plasmonic integrated circuits in the microwave frequencies.

Digital Noise-Coupling Technique for Delta–Sigma Modulators With Segmented Quantization

A digital noise-coupling technique for delta-sigma modulators with a high-resolution quantizer is presented. The proposed technique divides the outputs of the quantizer into an MSB segment and an LSB segment. The MSBs are directly fed to the modulator input, whereas the LSBs are used as the quantization noise for noise coupling. After the digital postprocessing, the MSBs and the LSBs are then recombined. As a result, it preserves the benefit of increased quantization levels without suffering from the exponential growth of the dynamic element matching logic. The extra noise shaping introduced by the LSB feedback further reduces the quantization noise leakage caused by the mismatch between the analog and digital noise transfer functions, which allows a more relaxed operational amplifier design. This technique is simple to implement and well suited for low-power and wideband applications.

A Multibit Delta–Sigma Modulator With Double Noise-Shaped Segmentation

This brief proposes a low-power architecture for a discrete-time (DT) delta-sigma modulator to take full advantages of increased quantization levels. In the proposed architecture, noise-shaped segmentation is applied to both the quantizer and the feedback digital-to-analog converter to maintain a high resolution and a high linearity and, at the same time, keep the hardware complexity low. This leads to a significantly reduced output swing of the integrator to minimize the slewing-related distortion in a DT implementation. The resulting uniform linear settling behavior can tolerate a relatively large settling error without degrading the performance, which greatly relaxes the bandwidth requirement of the op-amp design. The reduced output swing also allows the use of low-gain amplifiers, which is particularly attractive for an advanced technology in which the intrinsic gain of the transistor is degraded. The proposed architecture is analyzed and verified through simulation.

Analysis of Current Efficiency for CMOS Class-B

This paper focuses on the study of current efficiency in CMOS class-B LC oscillators. Exact expressions for current efficiency have been derived for the class-B oscillator. Theoretically, to achieve optimal figure-of-merit (FoM), the current efficiency in class-B oscillators is between 0.60 and 0.85, which revises the common assumption that current efficiency in all class-B oscillators is equal to 2/π. According to the theoretical analysis, the character of the tail capacitance and the boundary between current-limited regime and voltage-limited regime are discussed as well. A closed-form FoM expression is given with comparisons among different oscillators (including the traditional class-B, the AC-coupled class-B and the class-C), which show that the current efficiency of the two kinds of class-B oscillators is identical and the current efficiency of class-C oscillators is between 0.85 and 1. It is also shown that the main difference between the performances of these oscillators lies in voltage efficiency rather than current efficiency.

LC

The scalable modeling of CMOS integrated stacked millimeter wave transformer is presented. The model parameters are only related to the layout and process data. So this model is scalable with the two factors. We provide simple and accurate expressions for the self-inductance, mutual coupling inductance, oxide capacitance and the mutual coupling capacitance. High frequency effect and thick metal effect are considered, so the model is accurate at high frequency and can be used at millimeter wave IC design. The model is generated by these equations directly, and no further fitting or optimization is required. The model is verified by 65nm and 40nm CMOS technology transformers. We compare S-parameters, self-inductance of each coil, and coupling coefficient. A very close agreement has been obtained.

Oscillators

This paper presents a low-power intermediate frequency (IF) limiting amplifier (LA) and received signal strength indicator (RSSI). The LA and RSSI are designed for ZigBee™ receiver at 2MHz IF. To save power, two local loops for offset correction are used in LA chain and a sensitivity of -56dBm is achieved. Each LA gain stage employs cascade diodes load to avoid driving the diode load into velocity saturation region. The indication rang is 50dB within ±2dB linearity error. The core area is 0.11×0.31mm2 using a SMIC 0.18-μm CMOS technology. The overall power consumption is 1mW from a 1.8V supply voltage.

Scalable modeling of layout parameters in CMOS integrated stacked millimeter wave transformer

In this brief, a high-resolution successive-approximation-register analog-to-digital-conversion architecture for biomedical data acquisition is proposed. A filtered least-significant-bit segment is employed as a dither to improve the resolution. Theoretical analysis and behavioral simulations show that the error of a most-significant-bit segment can be converted into shaped noise if the input signal is sufficiently small. The proposed self-dithering technique can be used, together with averaging, to improve the signal-to-noise ratio and the differential nonlinearity (DNL) performance. The performance improvement is similar to that of a conventional nonsubtractive scheme using a uniform deterministic dither but with simplified hardware and reduced computation complexity.

A 1mW CMOS limiting amplifier and RSSI for ZigBee™ applications

A single-channel asynchronous successive approximation register analog-to-digital converter with a dual-trial instantaneous switching scheme is presented in this brief. The proposed architecture uses two capacitive digital-to-analog converter (DAC) arrays to generate two possible outputs while the comparator is in the regeneration process. Two comparators are assigned to each DAC to alternately switch between the compare phase and the reset phase. Such an approach allows the overlapping of the DAC settling, the comparator reset, and the comparator regeneration, which significantly improves the conversion speed. Furthermore, the random nature of the internal channel selection converts the mismatches between both channels into wideband noise, which improves the spurious-free dynamic range.

Self-Dithering Technique for High-Resolution SAR ADC Design

This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μ W, while the digital part consumes only 203 μ W.

A Speed-Enhancing Dual-Trial Instantaneous Switching Architecture for SAR ADCs

This paper presents a high resolution tuning scheme for the LC digitally-controlled-oscillator (DCO) based on desensitized tail capacitance tuning. The sensitivity of the oscillation frequency to the tail capacitance is quantitatively analyzed. The impact of the tail capacitance on the phase noise is qualitatively discussed. Our analysis and simulation results show that both the phase noise and the resolution can be improved simultaneously if the tail capacitance value is properly designed. A 2.4 GHz DCO designed in 65-nm CMOS technology is simulated for demonstration. The tuning resolution can be improved by a factor of 20, and the phase noise at 1 MHz offset can be improved by 2 dB.