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Dive into the research topics where Fujiwara Hirokazu is active.

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Featured researches published by Fujiwara Hirokazu.


Materials Science Forum | 2011

Reverse Electrical Characteristics of 4H-SiC JBS Diodes Fabricated on In-House Substrate with Low Threading Dislocation Density

Fujiwara Hirokazu; Masaki Konishi; Toyokazu Ohnishi; Tutomu Nakamura; Kimimori Hamada; Takashi Katsuno; Yukihiko Watanabe; Takeshi Endo; Takeo Yamamoto; Kazuhiro Tsuruta; Shoichi Onda

The impacts of threading dislocations, surface defects, donor concentration, and schottky Schottky barrier height on the reverse IV characteristic of silicon carbide (SiC) junction barrier schottky Schottky (JBS) diodes were investigated. The 100 A JBS diodes were fabricated on 4H-SiC 3-inch N-type wafers with two types of threading dislocation density. The typical densities are were 0.2×104 and 3.8×104 cm-2, respectively. The improvement of vIt was found that variations in the leakage current and the high yield of large area JBS diodes werecould be were obtained improved by using a wafer with a low threading dislocation density. In the range of low leakage current, the investigation shows showed a correlation between leakage current and threading dislocation density.


Materials Science Forum | 2012

Impact of Surface Morphology above Threading Dislocations on Leakage Current in 4H-SiC Diodes

Fujiwara Hirokazu; Takashi Katsuno; Tsuyoshi Ishikawa; Hideki Naruoka; Masaki Konishi; Takeshi Endo; Yukihiko Watanabe; Kazuhiro Tsuruta; S. Onda; A. Adachi; Masaru Nagao; Kimimori Hamada

The impact of threading dislocation density on the leakage current of reverse IV characteristics in 1.2 kV Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSDs), and PN junction diodes (PNDs) was investigated. The leakage current density and threading dislocation density have different positive correlations in each type of diode. For example, the correlation in SBDs is strong, but weak in PNDs. The threading dislocations were found to be in the same location as the current leakage points in the SBDs, but not in the PNDs. Nano-scale inverted cone pits were observed at the Schottky junction interface in SBDs, and it was found that leakage current increases in these diodes due to the concentration of electric fields at the peaks of the pits. These nano-scale pits were also observed directly above threading dislocations. In addition, this study succeeded in reducing the leakage current variation of 200 A-class JBSDs and SBDs by eliminating the nano-scale pits above the threading dislocations. As a result, a theoretical straight-line waveform was achieved.


Archive | 2010

VERTICAL TYPE SCHOTTKY DIODE

Konishi Masaki; Fujiwara Hirokazu; Watanabe Yukihiko; Katsuno Takashi; Yamamoto Takeo; Endo Takeshi


Archive | 2010

SEMICONDUCTOR DEVICE WITH SCHOTTKY BARRIER DIODE, AND METHOD OF MANUFACTURING THE SAME

Endo Takeshi; Yamamoto Takeo; Konishi Masaki; Fujiwara Hirokazu; Katsuno Takashi; Watanabe Yukihiko


Materials Science Forum | 2011

New Separation Method of Threading Dislocations in 4H-SiC Epitaxial Layer by Molten KOH Etching

Takashi Katsuno; Yukihiko Watanabe; Fujiwara Hirokazu; Masaki Konishi; Takeo Yamamoto; Takeshi Endo


Archive | 2015

MANUFACTURING METHOD FOR INSULATION GATE TYPE SEMICONDUCTOR DEVICE AND INSULATION GATE TYPE SEMICONDUCTOR DEVICE

Saito Jun; Fujiwara Hirokazu; Ikeda Tomoharu; Watanabe Yukihiko; Yamamoto Toshimasa


Archive | 2012

METHOD OF SPECIFYING DEPTH OF EMERGENCE OF DISLOCATION

Katsuno Takashi; Watanabe Yukihiko; Konishi Masaki; Morimoto Atsushi; Fujiwara Hirokazu; Morino Tomoo; Endo Takeshi


Archive | 2016

Herstellungsverfahren einer Halbleitereinrichtung des isolierten Gatetyps und Halbleitereinrichtung des isolierten Gatetyps

Saito Jun; Fujiwara Hirokazu; Ikeda Tomoharu; Watanabe Yukihiko; Yamamoto Toshimasa


Archive | 2016

Halbleitervorrichtung und Herstellungsverfahren für eine Halbleitervorrichtung

Saito Jun; Ikeda Tomoharu; Watanabe Yukihiko; Yamamoto Toshimasa; Fujiwara Hirokazu


Archive | 2015

METHOD FOR MANUFACTURING INSULATED GATE-TYPE SEMICONDUCTOR DEVICE, AND INSULATED GATE-TYPE SEMICONDUCTOR DEVICE

Saito Jun; Fujiwara Hirokazu; Ikeda Tomoharu; Watanabe Yukihiko; Yamamoto Toshimasa

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