Fulvio Spagna

A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS

The last few years have witnessed a rapid increase in serial IO data rates as well as number of IO ports in microprocessors. This trend, poses significant challenges to the serial IO design because of area and power budget limitations but, above all, by the need to achieve stringent bit error rates in the presence of interconnect constraints such as channel loss, impedance discontinuities induced by package and connectors, and crosstalk effects due to routing limitations in the package and on the motherboard. To effectively meet these challenges, the serial IO architecture has evolved to include more complex equalization schemes. Building on the previous work on a 4-tap DFE [1], this paper presents the design of a complete serial IO capable of operating up to 11.8Gb/s, and in particular, focuses on the integration of an adaptive equalizer and baud-rate CDR in the receiver of the serial IO.

A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS

Wide bandwidth communication between chips and modules has been achieved relying on large numbers of high-speed serial IOs. In this context, the most critical issue is overcoming the interconnect inter-symbol interference (ISI) while keeping low power dissipation and an energy-efficient power-scalable compact decision-feedback equalization (DFE) clearly fits the needs of this design space. In DFEs implemented in differential CML circuits with resistive load, the highest data rate is determined by the RC time constant at the CML summer output and the timing constraint that decision feedback must be settled within 1UI. Such a structure is not power scalable, and the requirement of precision passive resistor adds cost to such fine-feature process as 32nm. A current-integrating DFE summer was recently presented to eliminate resistive load and mitigate settling time constraint [1,2]. This paper presents a power-scalable 5-to-10Gb/s 4-tap DFE that provides further power savings by using three circuit techniques: 1:2 demultiplexed current-integrating summer, sense-amplifier (SA) latched-decision feedback, and fully differential current-recycled DACs (I-DACs).

A 90nm 1-4.25-Gb/s Multi Data Rate Receiver for High Speed Serial Links

This paper describes the design of a receiver that supports the operation from 1 to 4.25-Gb/s, enabling a single macro to satisfy different protocols. The receiver performs equalization to compensate for interconnect ISI, achieves 10 mV sensitivity at 4.25-Gb/s by using offset corrected amplification, and performs clock-data-recovery with a digital algorithm that controls a recovered clock out of a phase interpolator. The receiver has been validated in 90 nm CMOS with 45 mW at 1.1 V supply voltage and demonstrated to achieve link over 30-meter AGW24 cable at 3.125 Gb/s with BER<10-5.

Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery

On-Die features available for validation and test on an integrated circuit play a major role in evaluating the performance of the functionality being realized by the circuit in a post-silicon environment and can considerably reduce time to market of the end-product. In the case of high-speed IO, it is also important to note that the type of on-die hooks required to debug and validate the performance and robustness of the design depend on several factors, of which the type of I/O architecture chosen plays a key role. In order to support high data rates, the serial I/O design in this paper implements a receiver with adaptive equalization engine for the compensation of inter-symbol interference (ISI) and real-time environmental changes (temperature and voltage). This paper describes the debug hooks and their usage models in such a high-speed I/O designed using a 32nm CMOS process. These hooks have been tested in the lab and proven to be very useful. While the main focus of the paper is to describe the hooks, how they are used in the lab for observing the robustness in the dynamic behavior of the adaptive loops and the measurement results; the reader is also provided with a brief insight into the equations describing the loops behavior together with a description of the loops implementation details.

A 20 Mhz BiCMOS peak detect pulse qualifier and area detect servo demodulator for hard disk drive servo loop

With concentric data tracks separated radially by less than 10/spl mu/m, accurately detecting servo information on a magnetic disk is a crucial function of magnetic storage read channels. Valid servo Gray code confirms that the read/write head is in the servo sector. Servo bursts with different offsets from track centers provide vital track positioning information for the read/write head. The servo Gray code is a series of positive and negative pulses. The pulse qualifier outputs a RDS pulse for each pulse whose amplitude exceeds a user programmed threshold. Following the servo Gray code, the servo demodulator integrates over each servo burst, and outputs the magnitude of each integration. Trade-offs between power, area, and sensitivity to noise are considered in the servo demodulator architecture design. This implementation of a peak-detect pulse qualifier and an area detect servo demodulator is fabricated in 5V 0.8/spl mu/m BiCMOS. Total area of the two blocks is 2.15mm/sup 2/, and total power consumption of the two blocks is 130mW.

An Accurate and Efficient Link Analysis Methodology for High Speed I/O Design

This paper describes an accurate and efficient analysis methodology that enables circuit optimization directly guided by platform-level metric such as link eye margin. Prior to this work, such analysis was not feasible due to significant compute time required by complex circuit simulations. A new method of developing highly abstracted behavioral models of complex circuit blocks is a critical element of this analysis methodology. The method uses statistical signaling analysis and optimization capabilities coupled with behavioral modeling of I/O clocking, transmitter and receiver circuitry that are based on accurate circuit simulations. We also present measured data from products and test chips that show correlation between measured and modeled data within 10–15%. Finally, we describe how the methodology was used to optimize the design of a high speed serial link and achieve approximately 70% improvement in eye margins with limited design iterations.Copyright