G. Casarosa

The PixFEL project: development of advanced X-ray pixel detectors for application at future FEL facilities

The PixFEL project aims to develop an advanced X-ray camera for imaging suited for the demanding requirements of next generation free electron laser (FEL) facilities. New technologies can be deployed to boost the performance of imaging detectors as well as future pixel devices for tracking. In the first phase of the PixFEL project, approved by the INFN, the focus will be on the development of the microelectronic building blocks, carried out with a 65 nm CMOS technology, implementing a low noise analog front-end channel with high dynamic range and compression features, a low power ADC and high density memory. At the same time PixFEL will investigate and implement some of the enabling technologies to assembly a seamless large area X-ray camera composed by a matrix of multilayer four-side buttable tiles. A pixel matrix with active edge will be developed to minimize the dead area of the sensor layer. Vertical interconnection of two CMOS tiers will be explored to build a four-side buttable readout chip with small pixel pitch and all the on-board required functionalities. The ambitious target requirements of the new pixel device are: single photon resolution, 1 to 104 photons @ 1 keV to 10 keV input dynamic range, 10-bit analog to digital conversion up to 5 MHz, 1 kevent in-pixel memory and 100 μm pixel pitch. The long term goal of PixFEL will be the development of a versatile X-ray camera to be operated either in burst mode (European XFEL), or in continuous mode to cope with the high frame rates foreseen for the upgrade phase of the LCLS-II at SLAC.

Demonstrator of the Belle II online tracking and pixel data reduction on the High Level Trigger system

The future Belle II experiment will employ a computer-farm based data reduction system for the readout of its innermost detector, a DEPFET-technology based silicon detector with pixel readout. A large fraction of the background hits can be rejected by defining a set of regions of interest (ROIs) on the pixel detector sensors (PXD) and then recording just the data from the pixels inside the ROI. The ROIs are defined on an event by event basis by extrapolating back onto the PXD the charged tracks detected in the outer trackers (a four-layer double-sided silicon strip detector surrounded by a wire chamber). The tracks are reconstructed in real time on the High Level Trigger (HLT). The pixel detector is then read out based on the ROI information. A demonstrator of this architecture was under beam test earlier this year in DESY (Hamburg, Germany). The demonstrator was operated in an electron beam whose momentum was in the 2-6 GeV/c range with a typical trigger rate of a few kilohertz in a magnetic field of strength up to 1 T. The demonstrator consists of one pixel sensor and four silicon strip sensors arranged in a five-layer configuration mimicking the Belle II vertex detector. The detector readout was a scaled down version of the full Belle II DAQ + HLT chain. The demonstrator was used to detect the particles, reconstruct in real time the trajectories, identify the ROIs on the PXD plane and record the PXD data within. We describe the requirements and the architecture of the final system together with the results obtained with the demonstrator.

2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker

The high luminosity asymmetric e+e− collider SuperB, recently approved by the Italian Government, is designed to deliver a luminosity greater than 1036cm−2s−1 with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with an innermost layer of small radius (about 1.5 cm), resolution of 10 µm in both coordinates, low material budget (< 1% X0), and able to withstand a hit background rate of several tens of MHz/cm2. The ambitious goal of designing a thin pixel device matching these stringent requirements is being pursued with specific R&D programs on different technologies: CMOS MAPS, pixel sensors in vertical integration technology and hybrid pixels with small pitch and reduced material budget. The latest results on the characterization of the various pixel devices realized for the SuperB Layer0 will be presented.

Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests.

Design and TCAD simulations of planar active-edge pixel sensors for future XFEL applications

We report on the design and TCAD simulations of planar active-edge pixel sensors within the INFN PixFEL project. These devices are intended as one of the building blocks for the assembly of a multilayer, four-side buttable tile for X-ray imaging applications in future Free Electron Laser facilities. The requirements in terms of very wide dynamic range and tolerance to extremely high ionizing radiation doses call for high operation voltages. A comprehensive TCAD simulation study is presented, aimed at the best trade-offs between the minimization of the edge region size and the sensor breakdown voltage.

Belle II silicon vertex detector

The Belle II experiment at the SuperKEKB collider in Japan is designed to indirectly probe new physics using approximately 50 times the data recorded by its predecessor. An accurate determination of the decay-point position of subatomic particles such as beauty and charm hadrons as well as a precise measurement of low-momentum charged particles will play a key role in this pursuit. These will be accomplished by an inner tracking device comprising two layers of pixelated silicon detector and four layers of silicon vertex detector based on double-sided microstrip sensors. We describe herein the design, prototyping and construction efforts of the Belle-II silicon vertex detector.

Development of a Data Acquisition System for the Belle II Silicon Vertex Detector

Tohoku University, Miyagi, Japan The silicon-strip vertex detector in the Belle II experiment is one of essential detectors to search for physics beyond the Standard Model. To read out all 223,744 readout strips of the double-sided silicon strip detectors in high beam background, 1748 APV25 chips are employed for the frontend electronics. Hence, flash analog-to-digital conversion with high-density inputs is required on the back-end electronics. We developed prototypes of the back-end electronics and successfully performed a full integration test at the DESY electron beam line. In this paper, we report on the development of the prototypes and results from the beam test. Technology and Instrumentation in Particle Physics 2014, 2-6 June, 2014 Amsterdam, the Netherlands

First results of the Belle II Silicon Vertex Detector readout system

At the heart of the Belle II experiment at KEK (Japan), there will be a Vertex Detector (VXD) composed of 2 layers of DEPFET pixels (PXD) and 4 layers of double-sided silicon strip detectors (SVD). The latter use the APV25 front-end chip — originally developed for CMS — which is reading out the inner part of the SVD sensors through the Origami chip-on-sensor concept, including a state-of-the-art two-phase CO2 cooling. The whole system (including the full DAQ chain) was successfully tested in a beam at DESY in January 2014 and first results are presented here.

PixFEL: Enabling technologies, building blocks and architectures for advanced X-ray pixel cameras at the next generation FELs

The PixFEL project is conceived as the first stage of a long term research program aiming at the development of advanced instrumentation for coherent X-ray diffractive imaging applications at the next generation free electron laser (FEL) facilities. The project aims at substantially advancing the state-of-the-art in the field of 2D X-ray imaging through the adoption of cutting-edge microelectronic technologies and innovative design and architectural solutions. For this purpose, the collaboration is developing the fundamental microelectronic building blocks (low noise analog front-end with dynamic compression feature, high resolution, low power ADC, high density memories) and investigating and implementing the enabling technologies (active edge pixel sensors, high density and low density through silicon vias) for the assembly of a multilayer four side buttable tile. The building block design is being carried out in a 65 nm CMOS technology. The ambitious goal of the research program is the fabrication of an X-ray camera with single photon resolution, 1 to 104 photons @ 1 keV to 10 keV input dynamic range, 1 kevent in-pixel memory, 100 μm pixel pitch, and the capability to be operated at the fast (1 MHz or larger) rates foreseen for the future X-ray FEL machines.

PixFEL: development of an X-ray diffraction imager for future FEL applications

A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron Lasers) has been designed in a 65~nm CMOS technology. It consists of a