G. Davidson

Complexity reduction methods for vector excitation coding

Vector Excitation Coding (VXC) is based on a new and general source-filter modeling technique in which the excitation signal for a speech production model is encoded at very low bit-rates using vector quantization. Various speech coder structures which fall into this class have recently been shown to reproduce speech with very high perceptual quality. The primary drawback of VXC is the large amount of computation required in the process of selecting an optimal excitation signal. We present several schemes in this paper which substantially reduce search computation in VXC coders while retaining their remarkably high reconstructed speech quality.

Systolic architectures for vector quantization

A family of architectural techniques are proposed which offer efficient computation of weighted Euclidean distance measures for nearest-neighbor codebook searching. The general approach uses a single metric comparator chip in conjunction with a linear array of inner product processor chips. Very high vector-quantization (VQ) throughout can be achieved for many speech and image-processing applications. Several alternative configurations allow reasonable tradeoffs between speed and VLSI chip area required. >

Real-time vector excitation coding of speech at 4800 bps

In Vector Excitation Coding (VXC), speech is represented by applying a sequence of excitation vectors to a time-varying speech production filter with each vector chosen from a codebook using a perceptually-based performance measure. Although VXC is a powerful technique for achieving natural and high quality speech compression at low bit-rates, it suffers as other excitation coders do from a very high computational complexity. Recent research has shown that codebook search computation can be reduced to approximately 40 MFlops without compromising speech quality. However, this operation count still prohibits a practical real-time implementation of the coder using todays DSP chips. We present a real-time 4.8 kb/s Pulse Excitation VXC coder (PVXC) which achieves high reconstructed speech quality and incorporates new techniques which reduce the codebook search complexity to only 0.55 MFlops. The coder utilizes an optimized excitation codebook and a promising new interframe vector predictive LPC parameter quantization scheme. A preliminary implementation using a single floating-point signal processor is described.

Encoding of LPC spectral parameters using switched-adaptive interframe vector prediction (speech coding)

An efficient, low-complexity method called switched-adaptive interframe vector prediction (SIVP) has been developed for linear predictive coding (LPC) of spectral parameters in the development of low-bit-rate speech coding systems. SIVP utilizes vector linear prediction to exploit the high frame-to-frame redundancy present in the successive frames of LPC parameters. When SIVP is combined with scalar quantization, it has been found that the LPC parameter bit rate required to achieve high-quality synthetic speech is only 1300 b/s. With vector quantization, the bit-rate can be reduced even further (to 1000 b/s) without introducing any perceivable quantization noise in the reconstructed speech.<<ETX>>

Multiple-stage vector excitation coding of speech waveforms

An approach to vector-excitation-coding (VXC) speech compression utilizing multiple-stage vector quantization (VQ) is considered. Called multiple-stage VXC (MSVXC), this technique facilitates the use of high-dimensional excitation vectors at medium-band rates without substantially increasing computation. The basic approach consists of successively approximating the input speech vector in several cascaded VQ stages, where the input vector for each stage is the quantization error vector from the preceding stage. It is shown that if a number of VQ stages is increased sufficiently, MSVXC can be expressed as a form of transform coding, in which the computationally intensive excitation codebook search is completely eliminated.<<ETX>>

Application of a VLSI Vector Quantization Processor to Real-Time Speech Coding

The major obstacle which has limited the use of Vector Quantization (VQ) for real-time speech coding is the computationally demanding codebook-search algorithm. The essential task of this algorithm, pattern matching, has several properties which make it amenable to VLSI realization using a highly concurrent processor architecture. A VLSI pattern-matching chip provides the essential building-block for a specialpurpose codebook-search processor (CSP). The CSP can serve as a generic architecture for a variety of VQ-based speech coding applications. This paper reports on a working VQ processor for speech coding based on a first generation VLSI chip that efficiently performs the essential pattern-matching operation needed for the codebook-search process. Furthermore, the CSP architecture, using this chip, has been successfully incorporated into a compact single-board Vector PCM implementation which operates at rates between 7 and 18 kbits/s. A real-time Adaptive Vector Predictive Coder system using the CSP and augmented by a TMS-32010 programmable signal processor has been designed and recently implemented. We describe the structure of these two VQ coders and present experimental results obtained using the single-board Vector PCM coder.

A systolic vector quantization processor for real-time speech coding

The architecture and implementation of a novel VLSI bit-level systolic Vector Quantization processor is described. This architecture offers very high data throughput for real-time processing applications. Given a codebook of sizeNand dimensionk, an input vector can be quantized everyNclock cycles, compared to O(kN) cycles for a Single-Instruction, Single-Data (SISD) machine. Any distortion measure which can be expressed as a Euclidean vector inner product can be computed with this array.

Real-time speech compression with a VLSI vector quantization processor

Vector Quantization is an attractive block coding scheme which allows more efficient use of a given channel capacity. The computational complexity of the codebook search, however, limits the practical applications of Vector Quantization -- especially in real-time situations. This paper presents a special purpose processing architecture which supports real-time search of large codebooks. The core of the computation required for a squared-error distortion measure is accomplished using a VLSI pattern matching chip. We describe a pipeline architecture which reduces the effective computation time for a single vector component to one period. The chip supports a selectable vector dimension of 2, 4, 8, or 8 and can be used with any codebook size consistent with the input vector rate and the chips throughput. We have built and tested a 4-micron NMOS chip which supports up to four million squared-error distance calculations per second. We outline three approaches to real-time Vector quantization which use this chip to do the pattern matching: two waveform coding processors using Vector Pulse Code Modulation and Adaptive Vector Predictive Coding, and a novel approach to rapid codebook design.

4800 B/S Speech Compression Techniques for Mobile Satellite Systems

This paper will discuss three 4800 bps digital speech compression techniques currently being investigated for application in the mobile satellite service. These three techniques, vector adaptive predictive coding, vector excitation coding, and the self excited vocoder, are the most promising among a number of techniques being developed to possibly provide near-toll-quality speech compression while still keeping the bitrate low enough for a power and bandwidth limited satellite service.