G. E. Georgiou

A symmetric submicron CMOS technology

A CMOS process is described that is designed to optimize the transistor characteristics of the n-channel and p-channel devices simultaneously. This is achieved by making the n- and p-channel devices symmetric in channel doping, junction depths, sheet resistivities and threshold voltages. The resulting devices have CoSi2source/drains with sheet resistivities of 1.5-2 Ω/square, n+ and p+ polysilicon/TaSi2gate structures, Threshold voltages of 0.4 V and 1.5 µm separation between active to tub-edge regions. Diode characteristics of the CoSi2/n+ and CoSi2/P+ are determined to be as good as non-silicided silicon junctions. Maintaining the proper doping for the connected n+ and p+ polysilicon/silicide gates is demonstrated. Ring oscillator delays of 110 ps at 3.5 V are observed for devices with 0.5 µm channel lengths. The ring oscillator circuits are still operational at power supply voltages of 1.0 V due to the low threshold voltage of the transistors.

InP D-HBT IC's for 40 Gb/s and higher bitrate lightwave transceivers

The combination of device speed (f/sub T/, f/sub max/>150 GHz) and breakdown voltage (V/sup bcco/ of about 10 V), makes the double heterojunction InP-based HBT (D-HBT), a very attractive technology to implement the most demanding analog functions of 40 Gb/s transceivers. This is illustrated by the performance of a number of InP D-HBT circuits including millimeter-wave low phase-noise VCOs up to 146 GHz, low jitter 40 Gb/s limiting amplifiers, a 40 Gb/s driver amplifier with 4.5 V differential output swing and distributed pre-amplifiers with up to 1.4 THz gain-bandwidth.

Compact InP-based HBT VCOs with a wide tuning range at W- and D-band

Compact monolithic integrated differential voltage-controlled oscillators (VCOs) operating in W-band were realized using InP-based heterojunction bipolar transistors (HBTs). The oscillators, with a total chip size of 0.6 by 0.35 mm/sup 2/, are based on a balanced Colpitts-type topology with a coplanar transmission-line resonator. By varying the voltage across the base-collector junction of the HBT in the current mirror and by changing the current in the VCO, the oscillation frequency can be tuned between 84 and 106 GHz. At 100 GHz, a differential voltage swing of 400 mV is obtained, which should be sufficient to drive 100 Gb/s digital logic. By combining the balanced outputs of a similar differential VCO in a push-push configuration, a compact source with close to -10 dBm output power and a tuning range between 138 and 150 GHz is obtained.

Fabry-Perot diaphragm fiber-optic sensor

The general theory of a diaphragm fiber-optic sensor (DFOS) is proposed. We use a critical test to determine if a DFOS is based on Fabry-Perot interference or intensity modulation. By use of the critical test, this is the first design, to the best of our knowledge, of a purely Fabry-Perot DFOS, fabricated with microelectromechanical system technology, and characterized as an audible microphone and ultrasonic hydrophone with orders of improvement in signal-to-noise ratio.

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock data recovery (CDR) circuit is a key element for broad band optical communication systems at 40 Gb/s. We report a 40Gb/s CDR fabricated in Indium-Phosphide heterojunction bipolar transistor (InP HBT) technology using the more robust architecture of a phase lock loop with a digital early-late phase detector. The faster (compared to SiGe) InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This in turn reduces the circuit complexity (transistor count) and VCO requirements. The integrated IC includes an on-chip LC VCO and on-chip clock dividers to drive an external DEMUX and low frequency PLL control loop. On-chip limiting amplifier buffers are included for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed signal IC operating at the clock rate of 40 GHz. We describe the chip architecture and measurement results.

An InGaAs/InP HBT differential transimpedance amplifier with 47 GHz bandwidth

In this paper, we describe an InGaAs/InP heterostructure bipolar transistor differential transimpedance amplifier with high bandwidth of 47 GHz and high gain of 56 dB-ohms.

Thermal Stability Limits of Thin TiSi2 Effect on Submicron Line Resistance and Shallow Junction Leakage

TiSi 2 , the silicide most commonly used for a low resistivity self-aligned salicide process, must become thinner as the junction depth and poly-Si gate height decrease so as not to affect junction leakage and gate work function. The thermal stability of the thinner TiSi 2 during the back-end thermal process cycles, is an important concern. We report on the thermal stability of 300 to 100 A thin TiSi 2 on As, P, or BF, doped poly-Si to annealing at 750 to 850 o C for 10 to 30 min determined by the increase in the resistance of long 0.3 to 1.5 μm wide poly-Si meander lines

A 1:4 demultiplexer for 40 Gb/s fiber-optic applications

The demultiplexer (DEMUX) is a critical component of a fiber communication system. In order to satisfy increasing demands for data, fiber systems will employ several wavelengths carrying 40 Gb/s data in the near future. The requirements for such systems dictate that the DEMUX handle at least 4 channels of 10 Gb/s SONET/SDH data. The challenge is to build a 1:4 DEMUX that is both manufacturable and cost-effective to be integrated onto a receiver board. The authors describe a monolithic four-channel DEMUX for 40 Gb/s applications which uses an AlInAs/InGaAs HBT technology from a commercial foundry. Measurements demonstrate 40 Gb/s operation for 0.3 Vpp single-ended data input and 0.6 Vpp differential clock input.

Center embossed diaphragm design guidelines and Fabry-Perot diaphragm fiber optic sensor

This research established the design guidelines for center embossed diaphragms for micro-diaphragm fiber type sensors. Following the guidelines, a center embossed diaphragm fiber optic sensor (CE-DFOS) based on Fabry-Perot interference was designed and fabricated with micro-electro-mechanical system (MEMS) technology. The CE-DFOS was experimentally verified to have the designed intrinsic frequency, and demonstrated high sensitivity in parallel testing with a piezoelectric (PZT) sensor.

High-performance and high-uniformity InP/InGaAs/InP DHBT technology for high-speed optical communication systems

Recently, InP/InGaAs/InP double-heterostructure bipolar transistors (DHBT) have attracted a lot of attention in the realization of high-speed (>40 Gb/s) optical communication systems (G. Raghaven et al., IEEE Spectrum, Oct. 2000; Y. Baeyens et al, IEEE GaAs IC Symp. Tech. Dig., pp. 125-128, 2001; Y.K. Chen et al., IEDM Tech. Dig., 2001, and OFC Tech. Dig., 2002). Much progress has been made to improve the high-speed device performance and f/sub T/ values as high as 340 GHz have been reported (S. Lee et al, IEEE GaAs IC Symp. Tech. Dig., pp. 185-187, 2001; A. Fujihara et al., IEDM Tech. Dig., 2001; M. Ida et al., ibid., 2001.). However to our knowledge there have been few reports on the reproducibility, yield and robustness of these types of devices. For successful implementation of these devices in high speed ICs, in addition to high f/sub T/ and f/sub max/, a useful DHBT technology also needs to achieve low turn-on voltage V/sub ce,sat/, low knee voltage V/sub k/, high breakdown voltages BVCEO, BVCBO, and on-state breakdown voltage. Furthermore, excellent device yield, high circuit-performance and uniformity are required. Optimization of all these parameters is critical for any given technology to be practically useful. In this paper, we report on a high-yield, high performance InP/InGaAs DHBT process with excellent uniformity and reproducibility.