G. Gramegna

CMOS preamplifier for low-capacitance detectors

Abstract We present a new CMOS preamplifier and shaper, optimized for charge measurements with detectors of 0.1–1 pF capacitance. A self-adaptive biasing scheme with nonlinear pole-zero cancellation allows us to use an MOS device operated in the triode region as the DC feedback element while eliminating nonlinearity and sensitivity to supply, temperature, and process variations and accepting up to several μA leakage current. The circuit is continuously sensitive and requires no external adjustments to set the feedback resistance. Secondary sources of noise are minimized subject to a power dissipation constraint. Implemented in a 1.2 μm CMOS process, the preamplifier achieves an ENC of 35 e − + 58 e − /pF at 23 μs shaping time at a power consumption of about 3.2 mW. The integrated preamp/shaper has 50 ns shaping time and the ENC is 120 e − . It has 0.3% nonlinearity over an input dynamic range of 0–5 fC.

Steps towards the use of silicon drift detectors in heavy ion collisions at LHC

Abstract The inner tracking system of the ALICE detector for PbPb collisions at the LHC require a very good granularity in the innermost planes, due to the high particle density, up to 8000 particles per unit of rapidity. The silicon drift detectors are a very good candidate for this application, but up to now no large system using this technology has been industrially produced and operated in experiments. One of the first steps towards large scale production is the study of the doping uniformity in commercially available Si wafers. The understanding of doping fluctuations is of fundamental importance since they introduce deviations of the electron trajectories from the expected ones. In addition, it is also necessary to know the changes possibly introduced by different processing steps in the resistivity profiles. We report here the results of measurements of resistivity profiles for NTD silicon wafers both before and after processing.

Silicon drift detector; studies about geometry of electrodes and production technology

Abstract Having high spatial resolution and good energy response the silicon drift detector (SDD) finds specific applications in experimental physics. The aims of this project are: simplified detector production and operation, improved total-to-sensitivearea ratio and stable working conditions. We have started a systematic study which includes all elements of the device, the silicon wafer, the various electrodes, an improved technology and VLSI front-end electronics. Several prototypes have been produced and we are progressively testing them. We summarize here our program of work and present the results from the first drift structures tested.

Use of field plate in a linear silicon drift detector (SDD)

Abstract By use of extensive simulation, it is shown how a spread of the aluminium metallization over the interacthodic field oxide sensibly lowers the electric field at reverse biased p + n junctions, thus allowing use of higher drift fields. Based on the simulation results, the layout of a few test structures implementing alternative technological choices has been defined. The fabrication of these prototype detectors is presently in progress.

Statistical analysis and optimization of delay line chains for pixel readout electronics

Abstract An analytic model of the variance of the delay given by the delay line integrated in the Omega3/LHC1 pixel readout chip is proposed and verified with experimental data. This model can be used to further tune the design in order to maximise delay uniformity, thus optimising pixel detector time resolution.

A NOVEL CATHODE STRUCTURE FOR A SELF-BIASED LINEAR SILICON DRIFT DETECTOR

Abstract A novel cathode structure for a self-biased linear Silicon Drift Detector (SDD) is presented. The proper potential profile inside the fully depleted substrate is established by the voltage drop along a single cathode implanted across each external surface and arranged as a zigzag. Compared to other self-biased linear SDDs, the proposed structure features a uniform thermal distribution and optimizes the sensitive area. The Poissons equation together with the proper boundary conditions has been analytically solved in the 3D domain, and the solution has been validated by means of 3D simulation. A prototype based on this geometrical configuration has been manufactured at Canberra Semiconductor. The resistance spread of each portion which constitutes the implanted cathode has been measured and results within 2%.

Electrical and functional characterization of a novel self-biased linear silicon drift detector

Abstract We describe here a novel design of self-biased linear Silicon Drift Detector (SDD) which minimizes the dead area and ensures a uniform thermal distribution on the sensitive zone of the detector itself. The proper potential profile in the sensitive zone is established by the voltage drop along a single cathode which acts at the same time as a voltage divider and a field cathode. To verify the effectiveness of the novel working prinicple, a 2 × 3.4 cm2 preliminary prototype has been manufactured by Canberra Semiconductor. The static and dynamic characteristics of the proposed device confirm that the spatial resolution (20 μm) is not affected by the convergence of the cathode-strips if the voltage drop along them is linear.

A novel self-biased linear silicon drift detector

A novel linear silicon drift detector (SDD) is proposed in which the proper potential profile is established by the voltage drop along a unique p/sup +/ cathode implanted across the surfaces. This p/sup +/ implant, arranged in a zigzag shape, acts at the same time as voltage divider and field cathode and allows us to increase the sensitive area, improving also the uniformity of the thermal distribution and thus minimizing the fluctuation of the electron mobility on the sensitive zone of the SDD. The perturbations of the drift field due to the asymmetry of the strips constituting the zigzag cathode have been evaluated by solving analytically Poissons equation for a simplified model of the structure. Three-dimensional numerical simulations have been carried out to prove the negligible amount of the perturbation and the effectiveness of the proposed structure. Based on this principle, a prototype has been manufactured at Canberra Semiconductor Company. Dynamic measurements of the time-of-flight of an injected charge prove that the linearity of the prototype and the drift uniformity in the anode direction are very high.

An approach to the specification driven testing of analogue circuits

A fast method to test analogue circuits, featuring low testing cost is proposed here. The method is based on the properties of a set of parameters, /spl alpha//sub i/, easily measured by sampling in a few time points the circuit response to a rectangular pulse. Starting from the specifications defined on the circuit performances, it is possible to identify, via a statistical approach, the acceptability domain in the /spl alpha//sub i/ space. The faulty circuit is identified as its /spl alpha//sub i/ parameters do not belong to the acceptability region. The method was successfully applied to a second order low pass filter and to a CMOS load compensated Operational Transconductance Amplifier (OTA).