G. Herold

High-speed fault identification and protection for HVDC line using wavelet technique

This paper describes a new high-speed HVDC line protection using wavelet technique. Based on the representation of the travelling waves through wavelet modulus maxima, the protection criteria for HVDC fine are proposed. Simulations are carried out for testing the criteria. The influences of similar faults are discussed. The protection can detect the HVDC line fault well and identify the HVDC line fault clearly from the similar transients, such as commutation failure and AC single phase fault.

Feasibility of HVDC for Very Weak AC Systems with SCR below 1.5

This paper exposes the feasibility to connect high voltage DC transmission (HVDC) systems to very weak AC networks leading to short circuit ratios (SCR) lower than 1.5. The existing literature does not provide solutions for such a low SCR systems and often the HVDC expansions cannot grow enough as expected. The studies developed are for the short-term voltage stability phenomena, where a solution using the PSCAD/EMTDC program for a very weak AC network with SCR=1.0 is presented. The reactive power characteristics are shown since they are important to judge the behavior of solutions for AC/DC interactions

Simulation of a Power Electronic Based Fault Current Limiter (FCL) in Case of Different Faults

The effects of a fault current limiter (FCL) on different types of faults in a three-phase network are presented in this paper. The FCL is based on a six-pulse thyristor rectifier with a freewheeling diode. Parallel to the three branches of the rectifier a further thyristor branch is added to handle faults with connection to earth. The FCL is directly connected to a transformers neutral terminal. For the simulations in Matlab/Simulink a simple network is used

18-pulse cascaded-multilevel-converter

This paper presents an 18-pulse cascaded-multilevel-converter. With this inverter it is possible to generate AC voltages with low distortions in fundamental frequency modulation. Therefore differing voltage levels of multiple DC sources are added. Because of the topology of the inverter, all sources are balanced.

Comparison of different calculation methods for a power semiconductor based interphase power flow controller

In this paper a new dynamic interphase power flow controller (DIPFC) calculated in state space is described and compared with a fundamental-component based model. The analytic calculation in state space is based on a transformation into space-phasor and zero-sequence components. Accordingly the entire system is divided into orthogonal networks for each switching status. The resulting state-space descriptions can be coupled into a linear inhomogeneous boundary value problem utilizing the periodic switching sequence in steady-state. The solution can be transformed back into natural coordinates. Therefore the entire system and all time functions can be calculated analytically. Finally the analytic method is verified using a fundamental-component model calculating the fundamental impedance of the switched inductance by an evaluation of the Fourier coefficient integral.

Compensation, stability and losses in the presence of wheeling transactions with use of FACTS devices

Integration of FACTS devices and wheeling transactions into SCADA systems is investigated. The SVC, TCPS and UPFC are explained and modelled. Devices, policies and accounting methods are incorporated into PF and OPF algorithms. In two case studies, the accounting methods are analysed and compared for a wheeling contract across a transmission line. With the aid of FACTS devices the power flow can also be forced along the physical contract path in networks, thereby shielding other network participants. A case study on the 39 bus IEEE New England power system shows that FACTS devices can be used for an electronic fence during wheeling transactions. Accounting methods are shown. The stability and operating cost of the grid are investigated. It is found that TCPSs and UPFCs introduce nonconvexities, causing OPF difficulties.

The generation of symmetrical space phasors compared with the selective harmonic elimination method of multilevel converters

The basic concept of a multilevel converter is to synthesize a staircase voltage wave-form by the use of several lower voltage DC sources. Capacitors, batteries, fuel cells and photovoltaic modules can be used as DC sources. A multilevel converter has several advantages, like a high voltage quality and low electromagnetic compatibility problems. Two different modulation schemes for multilevel inverters will be analyzed and compared in this paper: The well known selective harmonic elimination method and the generation of highly pulsating space phasors.

A Dynamic Fault Current Limiter (DFCL)

A dynamic fault current limiter (DFCL) based on a six-pulse thyristor rectifier is presented in this paper. With this device several possibilities are given to limit and even control fault currents. On the one hand it can switch off the limited fault current very fast by blocking the firing pulses on the other hand it is possible to have only a slight effect on the steady short-circuit current, if one chooses the right control setting. Further the DFCL is able to set the magnitude of the fault current or the r.m.s. value respectively to a free selectable value by changing the firing angle.

Unsymmetrical operation of a DIPFC to reduce network interactions

In this paper an unsymmetrical operating dynamic interphase power flow controller (DIPFC) is described with a fundamental-component based model. The unsymmetrical control of this thyristor controlled FACTS device can be used to decouple the symmetrical components (positive-, negative- and zero-sequence component) of two connected arbitrary network notes. In an example network it is shown how the power flow between two networks can be regulated with the DIPFC and how the negative- and the zero-sequence voltages are reducible if one busbar is supplied with an unsymmetrical voltage.

Twelve-pulse multilevel current source inverters for fundamental frequency switching schemes

Due to several reasons current source inverters (CSI) are seldom used compared to the voltage source inverter (VSI) principle. On the one hand they need reverse blocking semiconductors, on the other hand their DC-link element is an inductor. Furthermore the topology is affected by the unavoidable resonant behaviour of its output network because of the necessary output capacitors. Until now all efforts to avoid the excitation of this resonance were switching scheme based. This paper provides the time domain solution for a twelve-pulse topology that is by its principle able to avoid the lowest order harmonics and can therefore be operated with every switching scheme, even fundamental frequency ones.