G. Jack Lipovski

An overview of the Texas reconfigurable array computer

This paper presents an overview of TRAC and then discusses the systems suitability for some promising applications: Monte Carlo techniques, numerical solutions to linear systems, and data base applications.

Packet switching in banyan networks

This paper presents a formal scheme for addressing base and apex nodes in SW-banyan networks. This scheme is used for routing packets in the network. Packet-switching, in conjunction with the the circuit-switch mode of operation, offers a very flexible and powerful mechanism for interprocess communication in the multiprocessor architectures based on the banyan networks. Finally, a fault-tolerent scheme for re-routing the packets in the network is presented, in case the packet encounters a faulty node in its path.

A question of style

Problems in the style of writing papers in Computer Architecture are delineated. A style of writing papers is proposed and some experiences with it are reported. This style may develop into a useful vehicle for reporting research in computer science.

Lookahead networks

A fail-soft and easily reconfigurable interconnection network is proposed that can function like a bus or like a shift register ring. Its performance as a bus exceeds the performance of an Ethernet, and its performance as a ring is similar to that of a distributed local computer network (DLCN). It can be reconfigured to a sufficient degree to prune out faults or to partition the network into subnetworks that can use possibly different protocols that are the most suitable for the subnetwork. Its multiple-level priority arbitration appears very useful for mixed voice-data networks, to give guaranteed response times to voice packets. Finally, though it functions like a bus or shift register ring, it is physically connected like a tree; so its cost is linear and delay is logarithmic with the number of processors in the network, and it is relatively easy to install in a building by using practices similar to those used in telephone line networks. This paper describes functions of network-level and some data link and physical-level protocols and develops several key mechanisms to achieve ease of diagnosis and fail-softness.

Semantic paging on intelligent discs

In order to apply Artificial Intelligence techniques like inferencing to large (10 9 -10 12 bit) data bases, an intelligent secondary memory is proposed that is capable of extracting a subgraph from a graph stored in it for further processing in a conventional or special purpose computer. The “pointer transfer” technique developed for CASSM is used to efficiently mark and output a subgraph stored in one file, and a simple technique is proposed to link parts of the subgraph stored on different files. Besides proposing a useful secondary memory system for applying Artificial Intelligence techniques to large data bases, this paper attacks one of the most difficult problems in distributed data base systems, which is the generation of “homomorphic query fragments” that automatically carry the query from one file to other files needed to resolve the query.

Resource allocation in rectangular CC-banyans

A resource allocation problem in a reconfigurable multicomputer architecture based on rectangular CC-banyan multistage interconnection network with arbitrary fanout and arbitrary number of levels is studied. Four commonly used problem structures such as ring, pipeline, broadcast and macropipeline are introduced and the mapping problem of these structures on the system model which is camparable to the resource allocation problem, is discussed. Analytic solutions to several mapping questions are presented and a new fault diagnosis method based on the solution to the problem of mapping the ring structure is given.

On virtual memories and micronetworks

We propose to use the microcomputer in a network to share I/O resources such as printers and archival memories. A model of a network is developed where computers correspond to edges of a graph. This model reflects the desired characteristics of the microcomputer organization. The advantage of virtual memory in these microcomputers is discussed. Herein, pages in the virtual memory are packets in the network. Packets and requests for packets are generated by page faults and packets are stored and forwarded by hardware like that to manage virtual memory pages. The paper discusses the strategy for a micronetwork and suggests an implementation of the hardware of such a network.

System demonstrator for board-to-board-level substrate-guided wave optoelectronic interconnections

We design and implement a system demonstrator based on vertical-cavity surface-emitting lasers, polymeric hologram grating couplers, and metal-semiconductor-metal photodetectors. As a preliminary experiment, we show the feasibility of board-to-board level substrate-guided wave optoelectronic interconnections in the real electrical system. First, we introduce a new architecture--centralized optical backplane--for board-to-board level interconnections. Second, the optoelectronic data channel is constructed compatible with standard PECL and capable of operating a 1.25 Gbps. Finally, it is employed to replace the conventional electrical data channel in a microprocessor system. We describe the performance of the entire system and discuss the future application of our centralized optical backplane in other electrical systems.

Timer Devices and Time Sharing

This chapter covers synchronization techniques, especially where the external world is considerably slower than the microcontroller. The chapter shows how to program these devices, how to use interrupts with them, and how they can be used to time multiplex the use of the processor. It describes hardware devices and their use for timing operations, and how these devices can be used to time multiplex the MPU. Further, the chapter shows how time sharing can be used with the Ariel operating system. It shows how a prepackaged and debugged operating system can provide time-sharing capabilities with significantly less effort. The timer and time-of-day hardware, time-sliced software, as well as Ariel service calls, provide the MMC2001 programmer an easy access to time synchronization. The time-of-day module (TOD) illustrates one of MMC200rs main design goals, which is to make the hardware as close as possible to the application, making it easy for an application to use standard time units like seconds. If timesharing is implemented using the real-time interrupt, a procedure can sleep a number of tick times. Finally, if Ariel is used, its service calls can be utilized to wait for a time, or until a time.

Parallel and Serial Input-Output

The interfacing of a microcomputer to almost any I/O system has been shown to be simple and flexible, using parallel and serial I/O devices. This chapter studies the different ways in which data can be passed through a port into or out of a microcontroller. The chapter introduces some 1/O software that moved data through a microcomputer, moved data into a buffer, and implemented a traffic light controller and IC tester using the simple I/O devices. Because timing is important to them, the chapter studies the timing of such program segments. It also presents indirect and serial I/O, which are especially attractive to the MMC2001 and other microcontroller systems. Next, the chapter considers how the ISPI can assist in serial I/O. The same approach can be used for designing an IC or an I/O system, and thus one develops an understanding of why it was designed as it was, and how it might be used. The chapter extends these techniques to analog interfacing, counters, communications interfacing, and display and magnetic recording chips.