G. K. Sharma

A quality-aware Energy-scalable Gaussian Smoothing Filter for image processing applications

Energy-efficient design is the prime requirement for modern portable devices as these devices employ compute intensive image/video processing cores which produces output for human consumption. The limited perception of human sense can be exploited to improve energy-efficacy via approximate designs. In this paper, a novel quality-aware Energy-Scalable Gaussian Smoothing Filter (ES-GSF) is proposed that significantly reduces energy requirement at the cost of slightly reduced quality. The energy scalability within ES-GSF is achieved by exploiting the relative significance of kernel coefficients existing on different boundaries. The ES-GSF computes significant boundaries for the given energy budget. Simulation results show that ES-GSF consumes 30.46% reduced energy with graceful quality degradation over the well-known existing architectures. Further, the ES-GSF can scale energy up to 65.05% when switched from high quality mode to energy-efficient mode. The efficacy of the proposed filter is demonstrated in edge detection where ES-GSF embedded edge detectors consume 29.9% less energy over the well-known existing architectures.

RICO: A low power repetitive iteration CORDIC for DSP applications in portable devices

Abstract COordinate Rotation DIgital Computer (CORDIC) is a unit that is widely used in the applications such as scientific calculators, signal/image processing, communication systems, robotics, 3-D graphics etc. exhibits huge computations and requires large power. This paper presents an approximate low power Repetitive Iteration CORDIC (RICO) architecture that calculates sine/cosine values very efficiently. In the proposed RICO, number of iterations are fixed and a specific iteration is repeated to reduce the implementation complexity. An additional comparator based logic that evaluates direction of micro-rotation within RICO reduces the data dependency between each iterations. The efficiency of the proposed RICO is evaluated in Discrete Cosine Transform (DCT) by implementing DCT using only three RICO units. Post-synthesis simulation results show that the proposed RICO achieves area and power savings of 37.19% and 94.05% respectively over the Conventional CORDIC at the cost of 29.39% increase in latency.

Energy scalable approximate DCT architecture trading quality via boundary error-resiliency

High energy-efficiency is an imperative requirement for todays portable multimedia devices. Most image/video processing devices employ energy-devouring Discrete Cosine Transform (DCT) unit that limits their performance. We propose a novel low-complexity DCT architecture that exploits non-significance-driven complexity reduction techniques namely neighbor pixel similarity (NPS) and constant multiplication factor (CMF). Further, quality-energy tradeoff is achieved via error-resiliency at image-boundaries. We also present a novel quality metric PMSE (Perceivable Mean Square Error) that quantifies perceivable error. Our architecture consumes 49.2% less energy at the expense of 1.43dB less PSNR and requires only 45.4% area over well-known DCT architectures.

An area and performance aware ECG encoder design for wireless healthcare services

Modern wearable devices demand low power high performance medical signal monitoring to achieve efficient and reliable health-care services. The electrocardiogram (ECG) signal which is used to diagnose heart diseases requires 24 hour monitoring. Efficient VLSI implementation of lossless ECG encoder is the critical requirement in wireless health care services. This paper presents an area efficient and high performance lossless ECG encoder that utilizes a single stage Huffman table to provide compressed ECG data. In the proposed ECG encoder architecture, low range of ECG data is encoded via small Huffman table whereas out of range data is segmented into upper and lower parts. These upper and lower parts are encoded by the same Huffman table in the two consecutive clock cycles. This architecture is implemented in MATLAB and simulated with MIT-BIH Arrhythmia database. The simulation results of the proposed ECG encoder show 72.87% more compression over the existing ECG encoder. To evaluate the hardware efficiency, the encoder is implemented in Verilog and synthesized with Synopsys Design Compiler using 90nm PDK. The results show that proposed encoder requires 12.11% less area and provides 2.1X improved performance over the existing encoder.

A low-cost energy efficient image scaling processor for multimedia applications

Image scaling is one of the widely used techniques in various portable devices to fit the image in their respective displays. Traditional image scaling architectures consume more power and hardware, making them inefficient for use in portable devices. In this paper, a low complexity image scaling algorithm is proposed. In the proposed algorithm, the target pixel is computed either by bilinear interpolation or by replication. The edge catching module in the architecture determines the method of computation which makes the design energy efficient. Further, algebraic manipulation is done and the resulting pipelined architecture shows significant reduction in hardware cost. In order to evaluate the efficacy, the proposed and existing algorithms are implemented in MATLAB and simulated using standard benchmark images. The proposed design is synthesized in Synopsys Design Compiler using 90-nm CMOS process which shows 43.3% reduced gate count and 25.9% reduction in energy over existing architectures without significant degradation in quality.