G. Krieger

Thermal response of integrated circuit input devices to an electrostatic energy pulse

The thermal response to an electro static discharge (ESD) pulse in silicon is presented and discussed using the three-dimensional heat equation and a set of boundary conditions that physically simulate the behavior of input protection mechanisms commonly used in integrated circuits. Waveforms that vary exponentially and linearly in time are quantitatively analyzed for a spatially localized hot spot and for an even distribution of heat along a circular periphery. The results confirm recent observations that deviation from the smooth and slow exponential waveform due to parasitic oscillations and coupling is a major cause of ESD related damage.

Diffused resistors characteristics at high current density levels-analysis and applications

Both heavily (source-drain) and lightly (well) doped diffused resistors used in modern CMOS integrated-circuit technologies are studied under high current density levels. The effects of high-field mobility degradation, space-charge limited-current, and charge-depletion narrowing (pinchoff) are discussed, and the related analytical solutions are derived and characterized. The applicability of the study to electrostatic discharge (ESD) protection networks, latchup protection circuitry, and output noise suppression resistors is addressed. Velocity saturation due to mobility degradation is found to be the prevailing mechanism, while space-charge limiting current and depletion narrowing have only limited effect on the lightly doped ones. The resulting saturation current densities allow proper resistor designs which can effectively limit ESD and latchup current into highly susceptible nodes and thus-improve overall circuit reliability, potential suppression of I/O switching noise is also discussed and shown to be more sensitive to the ratio between peak noise and steady-state currents. The experimental data confirm the theoretically predicted saturation velocity and critical field for the lightly doped case but show substantial discrepancy for the heavily doped layer. >

Moderately doped NMOS (M-LDD)-hot electron and current drive optimization

Short-channel NMOS transistors with moderately doped drain (10/sup 14/ cm/sup -2/), and variable sidewall oxide spacer thickness were fabricated and studied. The sensitivities of hot carrier degradation, current drive capability, and other device parameters to the sidewall spacer thickness were measured and evaluated. The results clearly indicate that a moderately doped drain (M-LDD) provides a stable and well-optimized device, compared to a conventional LDD transistor with substantially lower implant dose. A simple model, explaining the observations, is proposed and discussed. >

Shadowing effects due to tilted arsenic source/drain implant

The extent of n/sup +/ source/drain implant shadowing by the LDD (lightly doped drain) oxide sidewall spacer was studied for the commonly used 7 degrees wafer-to-implant beam tilt. A clear asymmetry in substrate current characteristics was observed between normal and reverse polarity, despite the use of 0 degrees tilt for the n/sup -/ LDD implant. The results suggest that 0 degrees tilt should be used for both n/sup -/ (LDD) and n/sup +/ (source/drain) implants. >

The effect of impact ionization induced bipolar action on n-channel hot-electron degradation

The relationship between the total impact ionization rate and the measured substrate current is analyzed, using short-channel NMOS devices. It is shown that holes that are injected into the source and turn on the parasitic source-bulk-drain bipolar may actually be a significant portion of the total impact ionization current. The authors explain how the commonly used model, which ignores this bipolar effect, can lead to incorrect predictions regarding hot-electron degradation. A related criterion for maximum source-drain voltage during accelerated stress is discussed and justified.<<ETX>>

Bipolar transistor action and transport effects relating to CMOS latchup

CMOS latchup holding characteristics are experimentally studied for a variety of lateral spacings and initial p- epi layer thicknesses. A transmission line model is used to explain the data and to point out the relationship between the geometric magnitudes and the corresponding holding current and voltage, mainly for shallow epi layers. Additional information regarding carrier transport during latchup and related high-injection effects is obtained from bipolar transistor measurements and analysis. It is concluded that the lateral bipolar is maintained active by carrier flow within the field-implanted region, unless the final epi is significantly thicker than the well depth. The major benefits of shallow epi are, therefore: 1) a shunting distributed path between the field-implanted layer and the heavily doped substrate, and 2) to increase the vertically injected current components that are diverted away from the latchup feedback loop.

The effect of emitter current crowding on CMOS latchup characteristics

Both static latchup and intrinsic p-n-p bipolar characteristics are compared and analyzed for various p-n-p-n test structures using a modern p-epi on p+CMOS technology. By varying the epi-layer thickness and the lateral spacing between the p+injector and the n-well boundary, it is shown that high-level injection and current crowding dominate the carrier transport inside the well under latchup conditions, especially when a shallow epi layer is used. As a result, a guideline for latchup-related design rules, applicable for large devices, which combines good latchup protection and a negligible penalty in area of performance, is proposed and discussed.

Thermal analysis of ESD-related hot spots (integrated circuits)

The thermal response to a microscopic hot spot, formed by an exponential electrostatic discharge (ESD) pulse, is analyzed and discussed, using a spherically symmetric Gaussian distribution to model the hot spot. A nonsingular solution to the three-dimensional heat equation, applicable to input protection devices in integrated circuits, is obtained. The resulting near-field temperature distribution can be used to study failures related to local silicon melting. >

An extension of the reciprocity theorem to include high-level injection conditions

The general proof of the Ebers-Moll reciprocity theorem is extended to include high-level injection conditions in bipolar base regions. The theorem, originally derived for the low-level case, is shown to be valid in the high-level limit, as long as the emitter injection efficiency is sufficiently high in both reciprocal configurations. >

An improved method to correlate measured circuit speed with simulation (CMOS gate arrays)

The relationship between the measured propagation delay of elementary circuits and the values obtained by circuit SPICE modeling was studied. Systematic and random variations of L/sub eff/ of the actual circuit from the modeled values L/sub eff/, which were extracted from separate test devices, were identified as a major source of error. The error was significantly reduced by an improved method to obtain the values of L/sub eff/ within the logic circuits, thus permitting accurate circuit performance modeling and the required technology optimization. >