G. Martin-Chassard

SPIROC (SiPM Integrated Read-Out Chip): dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35 m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100 ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memory content (time and charge on 2 gains). The data are then stored in a 4 kbytes RAM. A very complex digital part has been integrated to manage all theses features and to transfer the data to the DAQ which is described on [2].

SPIROC (SiPM Integrated Read-Out Chip): Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35 m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100 ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memory content (time and charge on 2 gains). The data are then stored in a 4 kbytes RAM. A very complex digital part has been integrated to manage all theses features and to transfer the data to the DAQ which is described on [2].

Silicon Photomultiplier integrated readout chip (SPIROC) for the ILC: Measurements and possible further development

The SPIROC chip is a dedicated very front-end ASIC chip for an ILC hadronic calorimeter technical prototype with Silicon Photomultiplier (or MPPC) readout. This ASIC is due to equip a 2,000-channel demonstrator in 2009. The SPIROC chip is the successor of the ILC SiPM ASIC presently used for the ILC AHCAL physics prototype, incorporating additional features like auto-triggering, pipelines, digitization as well as power pulsing. Realized in 0.35μm SiGe technology, it is designed in order to fulfill ILC final detector requirements of large dynamic range, low noise, low power consumption, high precision and large channel numbers. The SPIROC is a 36-channel chip. Each channel has bi-gain amplification, auto-triggering capability, a 16-bit depth analog memory array and a 12-bit wilkinson ADC. It allows time and charge measurements at the same time with digitized data results. The digitization is controlled and read out by the digital part of the chip. After the submission in June 2007, extensive measurements have been carried out to characterize the chip. This chip has been proven to be successful in calorimeter calibration as well as real physics experiments. Besides of the affirming measurement results, possible improvements are proposed in order to make the chip even more versatile in dealing with a large variety of Silicon Photomultipliers.

PARISROC, a photomultiplier array readout chip (PMm2 collaboration)

PARISROC is a complete readout chip, in AMS SiGe 0.35 mu m technology, for photomultipliers array. It is a front-end electronics ASIC which allows trigerless acquisition for the next generation of neutrino experiments. These detectors have place in megaton size water tanks and will require very large surface of photo-detection. An R & D program, funded by French National Agency for Research and called PMm2, proposes to segment the very large surface of photo-detection in macro pixels made of 16 photomultiplier tubes connected to an autonomous front-end electronics. The ASIC allows triggerless acquisition and only sends out the relevant data by network to the central data storage. This data management reduces considerably the cost of these detectors. This paper describes the front-end electronics ASIC called PARISROC which integrates totally independents 16 channels with a variable gain and provides charge and time measurement with a 12-bit ADC and a 24-bits Counter

HARDROC1, readout chip of the Digital HAdronic CALorimeter of ILC

HARDROC (HAdronic Rpc Detector ReadOut Chip) is the very front end chip designed for the readout of the RPC or Micromegas foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider. The very fine granularity of the ILC hadronic calorimeters (1cm2 pads) implies a huge number of electronics channels (4 105 /m3) which is a new feature of “imaging” calorimetry. Moreover, for compactness, the chips must be embedded inside the detector making crucial the reduction of the power consumption to 10 µWatt per channel. This is achieved using power pulsing, made possible by the ILC bunch pattern (1 ms of acquisition data for 199 ms of dead time). HARDROC readout is a semi-digital readout with two or three thresholds (2 or 3 bits readout respectively in hardroc1 and hardroc2) which allows both good tracking and coarse energy measurement, and also integrates on chip data storage. The 64 channels of the 2nd prototype, HARDROC2, are made of: • Fast low impedance preamplifier with a variable gain over 8 bits per channel • A variable slow shaper (50-150ns) and Track and Hold to provide a multiplexed analog charge output up to 15pC. • 3 variable gain fast shapers followed by 3 low offset discriminators to autotrig down to 10 fC up to 10pC. The thresholds are loaded by 3 internal 10 bit- DACs and the 3 discri outputs are sent to a 3 inputs to 2 outputs encoder • A 128 deep digital memory to store the 2*64 encoded outputs of the 3 discriminators and bunch crossing identification coded over 24 bits counter. • Power pulsing and integration of a POD (Power On Digital) module for the 5MHz and 40 Mhz clocks management during the readout, to reach 10µW/channel The overall performance of HARDROC will be described with detailed measurements of all the characteristics. Hundreds of chips have indeed been produced and tested before being mounted on printed boards developed for the readout of large scale (1m2) RPC and Micromegas prototypes. These prototypes have been tested with cosmics and also in testbeam at CERN in 2008 and 2009 to evaluate the performance of different kinds of GRPCs and to validate the semi-digital electronics readout system in beam conditions.

Subnano time to digital converter implemented in PARISROC for PMm2 R&D program

PARISROC is a complete read out chip, in a BiCMOS SiGe 0.35μm technology from AustriaMicroSystems, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and is part of a R&D program called PMm2. The ASIC integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a 10-bit Wilkinson ADC and a 24-bit counter. The time measurement is made of 2 complementary systems: a 24-bit gray counter (coarse time) with a step of 100 ns, and a double ramp TDC (fine time) with a 10-bit resolution and a measured precision of 425 ps RMS. Only the analog TDC will be explained in this paper by detailing the double ramp TDC architecture, the special cares and the first fine time measurements. One of the fine time TDC characteristics is the fact that the double ramp generator is common to all channels.

Digital part of PARISROC: A photomultiplier array readout chip

PARISROC is the front end ASIC designed to read 16 PMT for neutrino experiments. It’s able to shape, discriminate, convert and readout data in an autonomous mode. The digital part manages each channel independently thanks to 4 modules: top manager, acquisition, conversion and readout. Acquisition is in charge to manage the SCA with a depth of 2 for charge and fine time measurement. Coarse time measurement is made with a 24 bits gray counter. Readout module sends converted data of hit channels to an external system. Top manager controls the start and stop of the 3 others modules. The ASIC was submitted in June 2008.

PMm2 ASIC: PARISROC

PARISROC is a complete read out chip in AMS SiGe 0.35μm technology for photomultipliers array. It is made to allow triggerless acquisition for next generation neutrino experiments. The ASIC integrates 16 independent channels with variable gain and provides charge and time measurement with a 12-bit ADC and a 24-bits Counter.

Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays

CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

SPIROC: Design and performance of a dedicated very front-end for an ILC prototype Hadronic Calorimeter with SiPM

The SPIROC chip is a dedicated very front-end electronics to read out a prototype of the Analog Hadronic Calorimeter equipped with Silicon Photomultiplier (SiPM) for ILC (International Linear Collider). A first prototype of SPIROC has been fabricated in 2007 and a second version in 2010. Many test bench and test beam measurements have been performed showing a good overall behavior. However some limitations have been encountered. Another version has been submitted in February 2012 to correct these limitations and to improve the ASIC performances. After an exhaustive description of the ASIC, the performances will be presented in this paper.