G. Meddeler

A readout chip for a 64 x 64 pixel matrix with 15-bit single photon counting

A single Photon Counting pixel detector readout Chip (PCC) has been derived from previous work in the CERN RD19 collaboration for particle physics tracking devices, recently developed for high energy physics experiments. The readout chip is a 64 x 64 matrix of identical 170 {micro}m x 170 {micro}m cells. It is to be bump-bonded to an equally segmented 1 cm{sup 2} matrix of semiconductor sensors, e.g. Si or GaAs. Each readout cell comprises a preamplifier, a discriminator and a 15-bit counter. The input noise is 170 e{sup {minus}} rms. At the lowest nominal threshold of 1,400 e{sup {minus}} (5.1 keV in Si) the cells exhibit a threshold distribution with a spread before adjustment of 350 e{sup {minus}} rms. Each cell has a 5-bit register which allows masking, test-enable and 3-bit individual threshold adjust. After adjustment the threshold spread is reduced to 80 e{sup {minus}} rms. Absolute calibration of the electrically measured equivalent charge can be done once the readout chip is bump-bonded to a detector.

LHC1: A semiconductor pixel detector readout chip with internal, tunable delay providing a binary pattern of selected events

The Omega3/LHC1 pixel detector readout chip comprises a matrix of 128 × 16 readout cells of 50 μm × 500 μm and peripheral functions with 4 distinct modes of initialization and operation, together more than 800 000 transistors. Each cell contains a complete chain of amplifier, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Every cell can be individually addressed for electrical test and masking. First results have been obtained from electrical tests of a chip without detector as well as from source measurements. The electronic noise without detector is ∼ 100 e− rms. The lowest threshold setting is close to 2000 e− and non-uniformity has been measured to be better than 450 e− rms at 5000 e− threshold. A timewalk of < 10 ns and a precision of < 6 ns rms on a delay of 2 μs have been measured. The results may be improved by further optimization.

Development of a pixel readout chip compatible with large area coverage

Abstract A second version of the Omega pixel readout chip has been developed in order to make it compatible with large area coverage. Specific features of the new chip include a reset which can be applied immediately following a “false” trigger, an improved minimum strobe time of ∼ 100 ns, a readout clock rate of ∼ 20 MHz and tri-state buffers on the output data lines. The excellent performance figures of the first chip for noise (100 e rms without detector and 170 e rms with detector) and power consumption (30 μW/pixel) have been maintained. We demonstrate how with solder bump-bonding we can create hybrid “ladders” which hermetically cover an area of ∼ 5 mm × 50 mm. Potential problems of electrical matching and yield have been addressed and procedures are in place for selecting only “good” readout chips for mounting.

ICON, a current mode preamplifier in CMOS technology for use with high rate particle detectors

A current mode preamplifier named ICON is intended for use in experiments at high-rate hadron colliders. The transient response and noise performance have been analyzed. One chip has been made using an ICON circuit with resistive feedback to produce a preamplifier with a peaking time below 10 ns. This fast preamplifier has a gain of 870 mV/pC and a power dissipation of around 1 mW. Another chip was made which uses the ICON circuit as the front-end to a dual port analog memory. The noise measured is between 2500 e/sup -/ and 3000 e/sup -/. An important characteristic of ICON is that it can tolerate a detector leakage current of 10 mu A at the DC coupled input. Therefore, it is very suitable for silicon detector systems under several radiation conditions.<<ETX>>

First operation of a 72-k element hybrid silicon micropattern pixel detector array

Abstract We have constructed and tested silicon pixel detector arrays of 96 × 378 (36 288) sensor elements with 75 μm × 500 μm area. The low-noise signal processing circuit associated with each element occupies an identical area on a bump-bonded readout chip. The pixel cell response for ionizing particles is binary with an adjustable threshold between 4000 e − and 15 000 e − . Single chips, the array of 6 ladders and a double array have been characterized in particle test beams and in the Omega experiment WA97 at CERN. The two arrays together, staggered by ∼ 4 mm cover hermetically a 53 mm × 55 mm area with 72 576 pixels. The proportion of properly functioning pixels was 98% in the first 36 k pixel array and 80% in the second one. The ∼ 1% “always-on” pixels could be masked electronically. After masking the rate of “spurious noise hits” was −8 of the identified particle hits while with beam off no hits at all were recorded With a beam trigger most events consisted of a single cluster with a single hit. At the 8000 e − threshold an efficiency > 99% was measured. Tracks were reconstructed with a precision of 22 μm. The proportion of double hits (∼ 11%) depends only slightly on threshold and detector bias voltage, and for these double hits a precision of 10 μm on the particle position was obtained.

Experience with a 30 cm2 silicon pixel plane in CERN experiment WA97

Abstract A multi-chip, large area hybrid silicon pixel detector has been integrated in a particle physics experiment for the first time. The plane had 72K 75 μ m × 500 μ m sensor elements, covering a total area of about 30 cm 2 . It was constructed and characterized in a collaboration between heavy-ion experiment WA97 and R&D project RD19. Several such planes will be incorporated in a hyperon telescope, in order to improve tracking in the high multiplicity environment of central lead-lead collisions at the SPS. Results on the characterization of this detector in a proton beam at the Omega spectrometer at CERN are presented and discussed.

Progress in development of the readout chip for the ATLAS semiconductor tracker

The development of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS Semiconductor Tracker has entered a pre-production prototyping phase. Following evaluation of the ABCD2T prototype chip, necessary correction in the design have been implemented and the ABCD3T version has been manufactured in the DMILL process. Design issues addressed in the ABCD3T chip and performance of this pre-production prototype are discussed.

A readout chip for a 64/spl times/64 pixel matrix with 15-bit single photon counting

A single photon counting pixel detector readout chip (PCC) has been derived from previous work in the CERN RD19 collaboration for particle physics tracking devices, recently developed for high energy physics experiments. The readout chip is a 64/spl times/64 matrix of identical 170 /spl mu/m/spl times/170 /spl mu/m cells. It is to be bump-bonded to an equally segmented 1 cm/sup 2/ matrix of semiconductor sensors, e.g. Si or GaAs. Each readout cell comprises a preamplifier, a discriminator and a 15-bit counter. The input noise is 170 e/sup -/ rms. At the lowest nominal threshold of 1 400 e/sup -/ (5.1 keV in Si) the cells exhibit a threshold distribution with a spread before adjustment of 350 e/sup -/ rms. Each cell has a 5-bit register which allows masking, test-enable and 3-bit individual threshold adjust. After adjustment the threshold spread is reduced to 80 e/sup -/ rms. Absolute calibration of the electrically measured equivalent charge can be done once the readout chip is bump-bonded to a detector.

A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors

Abstract An analog memory array with 64 memory cells for each channel has been designed and manufactured in CMOS. A new skip logic controller allows to write at 66 MHz without dead time and to read out at a lower frequency simultaneously. The input circuit is charge-sensitive and integrates continuously. Pedestal nonuniformity is 1.4 mV rms from cell-to-cell and 3.5 mV rms between channels. The linearity range is −2.5 to +1.5 V, which corresponds to 11 bits. The chip has been used in a particle detection test.

Radiation hardness of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS semiconductor tracker

The radiation hardness requirements of the ABCD chip are driven by the radiation levels expected in the ATLAS SCT after 10 years of LHC operation, which are 10 Mrad of total ionising dose and 2×10 n/cm of 1 MeV eq neutron fluence for the displacement damages. The ABCD chip, comprising both analogue and digital circuitry and realised in a BiCMOS technology, is sensitive to ionisation effects as well as to displacement damages. The recent prototype of the ABCD chip, which meets all SCT requirements, has been irradiated separately with X-ray, neutrons from a nuclear reactor, and with 24 GeV protons. In the paper we present and discuss the radiation effects observed in the ABCD chip.