Gab Cheon Jung

An efficient line based VLSI architecture for 2D lifting DWT

This paper presents a line based VLSI architecture for real time processing of 2D lifting discrete wavelet transform (DWT). The architecture computes lifting operation based on state space representation and uses RPA (Recursive Pyramid Algorithm) scheme. To improve hardware utilization, the filter that is responsible for column operations of the first level performs both the row and column operations of the second and following levels. As a result, the architecture has the 66.7%-88.9% hardware utilization and requires only 9 multipliers and 12 adders for biorthogonal (9,7)/(5,3) filter, which is a smaller hardware complexity compared to that of other architecture with comparable throughput.

VLSI Implementation of Lifting Wavelet Transform of JPEG2000 with Efficient RPA(Recursive Pyramid Algorithm) Realization

This paper presents an efficient VLSI architecture of biorthogonal (9,7)/(5,3) lifting based discrete wavelet transform that is used by lossy or lossless compression of JPEG2000. To improve hardware utilization of RPA (Recursive Pyramid Algorithm) implementation, we make the filter that is responsible for row operations of the first level perform both column operations and row operations of the second and following levels. As a result, the architecture has 66.7--88.9% hardware utilization. It requires 9 multipliers, 12 adders, and 12N line memories for N × N image, which is smaller hardware complexity compared to that of other architectures with comparable throughput.

Efficient VLSI architectures for convolution and lifting based 2-d discrete wavelet transform

This paper presents efficient VLSI architectures for real time processing of separable convolution and lifting based 2-D discrete wavelet transform (DWT). Convolution based architecture uses partitioning algorithm based on the state space representation method and lifting based architecture applies pipelining to each lifting step. Both architectures use recursive pyramid algorithm(RPA) scheduling that intersperses both the row and column operations of the second and following levels among column operations of the first level without using additional filter for row operations of the second and following levels. As a result, proposed architectures have smaller hardware complexity compared to that of other conventional separable architectures with comparable throughput.

An efficient VLSI architecture for JPEG2000 encoder

This paper presents an efficient VLSI architecture of JPEG2000 encoder that has high performance with low hardware complexity. The proposed architecture performs RPA (recursive pyramid algorithm) based 2D lifting DWT operations with the reduction of processing elements and bit-plane parallel EBCOT (embedded block coded with optimized truncation) operations using one bit-plane coder and binary arithmetic coder per two bit-planes. Together with multi-level processing of DWT, it conducts multi-level EBCOT operations as soon as M lines of each wavelet subband are available, where M is column size of code block. As a result, it can have fast computation time and reduce memory requirement

An Efficient Rate-Distortion Optimization Scheme for JPEG2000

This paper describes an efficient PCRD (Post-Compres-sion Rate-Distortion) scheme for rate control of JPEG2000. The proposed method determines the rate constant in consideration of the decreasing characteristic of RD-slopes and conducts rate allocation about only coding passes excluded from the previous rate allocation. As a result, it can considerably reduce the number of operations and encoding time with nearly the same PSNR performance as the conventional rate control scheme of JPEG2000.

An efficient 2-D DWT processor architecture based on state space implementation technique

This work presents an efficient processor architecture which is constructed by filter bank or lifting scheme for real time processing of separable 2-D discrete wavelet transform (DWT). To achieve high efficiency, we use the partitioning algorithm based on the state space representation technique and RPA-like scheme. As a result, the architecture can reduce the critical path by the state space implementation. It has smaller hardware resources compared to that of other architectures with comparable throughput by the improvement of hardware utilization.