Gabriel Jiménez

AER tools for communications and debugging

Address-event-representation (AER) is a communications protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them in real time, while performing some processing. To develop and test AER based systems it is convenient to have a set of instruments that would allow to: generate AER streams, monitor the output produced by neural chips and modify the spike stream produced by an emitting chip to adapt it to the requirements of the receiving elements. In this paper we present a set of tools that implement these functions developed in the CAVIAR EU project

Two hardware implementations of the exhaustive synthetic AER generation method

Address-Event-Representation (AER) is a communications protocol for transferring images between chips, originally developed for bio-inspired image processing systems. In [6], [5] various software methods for synthetic AER generation were presented. But in neuro-inspired research field, hardware methods are needed to generate AER from laptop computers. In this paper two real time implementations of the exhaustive method, proposed in [6], [5], are presented. These implementations can transmit, through AER bus, images stored in a computer using USB-AER board developed by our RTCAR group for the CAVIAR EU project.

AER Neuro-Inspired interface to Anthropomorphic Robotic Hand

Address-event-representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for neuro-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The information transmitted is a sequence of spikes coded using high speed digital buses. These multi-layer and multi-chip AER systems perform actually not only image processing, but also audio processing, filtering, learning, locomotion, etc. This paper present an AER interface for controlling an anthropomorphic robotic hand with a neuro-inspired system.

A generalization of path following for mobile robots

Several authors have proposed some methods for applying path following in specific cases to mobile robots. When we try to extend the path following approach to the general problem several difficulties arise. We present a generalized technique to apply path following to a mobile robot with nonholonomic constraints. As an application example, we expose the case of mobile robots with a higher degree of manoeuvrability than the typical car-like robots. In particular we consider a robot that can turn around itself making a zero-radius turn; a case still not resolved as far as we know. Finally we propose a suitable control law for this example that ensures asymptotical convergence.

Inter-spike-intervals analysis of AER Poisson-like generator hardware

Address-Event-Representation (AER) is a communication protocol for transferring images between chips, originally developed for bio-inspired image-processing systems. Such systems may consist of a complicated hierarchical structure with many chips that transmit images among them in real time, while performing some processing (for example, convolutions). In developing AER-based systems it is very convenient to have available some means of generating AER streams from on-computer stored images. Rank order coding (ROC) and Poisson rate coding are the extremes of spikes coding. In this paper, we present a pseudo-random hardware method for generating AER streams in real time from a sequence of images stored in a computers memory. The Kolmogorov-Smirnov test has been applied to quantify that this method follows a Poisson distribution of the spikes. A USB-AER board, developed by our RTCAR group, have been used for the measurements. An example scenario of use under the EU CAVIAR project is presented.

On the AER convolution processors for FPGA

Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In these scenarios the visual information is divided into frames and each one has to be completely processed before the next frame arrives in order to warranty the real-time. A spike-based philosophy for computing convolutions based on the neuro-inspired Address-Event-Representation (AER) is achieving high performances. In this paper we present two FPGA implementations of AER-based convolution processors for relatively small Xilinx FPGAs (Spartan-II 200 and Spartan-3 400), which process 64×64 images with 11×11 convolution kernels. The maximum equivalent operation rate that can be reached is 163.51 MOPS for 11×11 kernels, in a Xilinx Spartan 3 400 FPGA with a 50MHz clock. Formulations, hardware architecture, operation examples and performance comparison with frame-based convolution processors are presented and discussed.

AER-based robotic closed-loop control system

Address-event-representation (AER) is an asynchronous protocol for transferring the information of spiking neuro-inspired systems. Actually AER systems are able to see, to ear, to process information, and to learn. Regarding to the actuation step, the AER has been used for implementing central pattern generator algorithms, but not for controlling the actuators in a closed-loop spike-based way. In this paper we analyze an AER based model for a real-time neuro-inspired closed-loop control system. We demonstrate it into a differential control system for a two-wheel vehicle using feedback AER information. PFM modulation has been used to power the DC motors of the vehicle and translation into AER of encoder information is also presented for the close-loop. A codesign platform (called AER-Robot), based into a Xilinx Spartan 3 FPGA and an 8051 USB microcontroller, with power stages for four DC motors has been used for the demonstrator.

SIRIUS: improving the maneuverability of powered wheelchairs

The indoor maneuverability of powered wheelchairs may be difficult or bothersome in several circumstances. In this paper, we describe an experimental powered wheelchair named SIRIUS, developed at the University of Seville, which introduces some simple but effective navigation aids. Special emphasis is placed on the implementation of recorded trajectory playback and in the shared control modes, i.e., the chairs guiding where both the user and the computer collaborate. Furthermore, SIRIUS is an open platform to essay another kinds of functional or navigational aids, because its hardware architecture is based on a commercial PC. This would permit many devices that are frequently needed by the chair driver to be integrated smoothly into the chair controller.

Analysis of channel utilization for controller area networks

In this paper, a model for the analysis of the CAN protocol is presented, extending the analysis already developed for fixed priority multiprocessors. Two cases are considered, which correspond to the main commercial devices. The model allows us to obtain some useful results for the design of CAN-based systems. The main conclusions are those regarding bus utilization, both total and per priority level. The results are validated using simulation. Finally, the real-time behavior is also briefly discussed.

On the designing of spikes band-pass filters for FPGA

In this paper we present two implementations of spike-based band-pass filters, which are able to reject out-of-band frequency components in the spike domain. First one is based on the use of previously designed spike-based low-pass filters. With this architecture the quality factor, Q, is lower than 0.5. The second implementation is inspired in the analog multi-feedback filters (MFB) topology, it provides a higher than 1 Q factor, and ideally tends to infinite. These filters have been written in VHLD, and synthesized for FPGA. Two spike-based band-pass filters presented take advantages of the spike rate coded representation to perform a massively parallel processing without complex hardware units, like floating point arithmetic units, or a large memory. These low requirements of hardware allow the integration of a high number of filters inside a FPGA, allowing to process several spike coded signals fully in parallel.