Gabriel M. Li

Advanced photolithographic process modeling and characterization via wafer flatness measurements

In this work critical dimension (CD) and site focal plane deviation (SFPD) measurements were made on a patterned resist test structure with 0.8 micron dense lines with a pitch of 1.6 micrometers . The CD and SFPD were tracked through all critical wafer processing steps. The range in SFPD was negligible throughout front end processing, with average SFPDs less than 0.25 microns. Significant increase in the mean and variance of SFPD was observed at later process modules. An increase in the SFPD directly reduces the focus budget, resulting in an increase in the variation of the CD across a field as well as a degradation of the resist profile. Within-field CD variation (3 sigma) for a SFPD of 0.05 micrometers was observed to be less than 0.03 micrometers (30 measurement sites within a field) whereas the three sigma CD variation for a SFPD of 3.8 micrometers was observed to be 0.45 micrometers . Two-dimensional and 3-D graphical correlations are presented, and the use of the SFPD/CD correlation technique to photolithographic process optimization is discussed.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Gigabit point-to-point data link system with cascaded optical fiber channels

A station implementing the Accredited Standards Committee (ASC) X3T9.5 fiber distributed data interface (FDDI) physical layer communications protocol standard can transmit and receive data simultaneously at a data rate of 100 Mb/s through a pair of optical fiber cables or fiber channels. Each station, with multiple physical layers and their associated fiber channels connected together in parallel, can transmit and receive data at a much higher rate. National Semiconductors physical layer (PHY) devices can be conveniently connected together to achieve a gigabit bandwidth point to point data link system, whereby the bandwidth is directly proportional to the number of PHY devices used.

Solving clock distribution problems in FDDI concentrators

This paper addresses the advantages of using a concentrator for inserting or removing a station onto or from the Fiber Distributed Data Interface (FDDI) ring. It gives an overview of the architecture of a FDDI concentrator. It highlights major data and clock distribution problems in a backplane bus. The main focus is a design example of a small and large concentrator using the National Semiconductor FDDI chipset. Different timing contraints such as setup and hold data and clock flight time and flight time cancellation are discussed in detail.