Gabriel Marchesan Almeida

An Adaptive Message Passing MPSoC Framework

Multiprocessor Systems-on-Chips (MPSoCs) offer superior performance while maintaining flexibility and reusability thanks to software oriented personalization. While most MPSoCs are today heterogeneous for better meeting the targeted application requirements, homogeneous MPSoCs may become in a near future a viable alternative bringing other benefits such as run-time load balancing and task migration. The work presented in this paper relies on a homogeneous NoC-based MPSoC framework we developed for exploring scalable and adaptive on-line continuous mapping techniques. Each processor of this system is compact and runs a tiny preemptive operating system that monitors various metrics and is entitled to take remapping decisions through code migration techniques. This approach that endows the architecture with decisional capabilities permits refining application implementation at run-time according to various criteria. Experiments based on simple policies are presented on various applications that demonstrate the benefits of such an approach.

Evaluating the impact of task migration in multi-processor systems-on-chip

This paper presents a Multi-Processor System-on-Chip platform which is capable of load balancing at run-time. The system is purely distributed in the sense that each processor is capable of making decisions on its own, without having relying by any central unit. All the management is ensured by a very tiny preemptive RTOS (run-time operating system) running on every processor which is mainly responsible for running and distributing tasks among the processing elements (PEs). The goal of such strategy is to improve the performance of the system while ensuring scalability of the design. In order to validate the concepts, we have conducted some experiments with a widely used multimedia application: the MJPEG (Motion JPEG) decoder. Obtained results show that the overhead caused by the task migration mechanism is amortized by the gain in term of performance.

Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach

The mapping of tasks to processing elements of an MPSoC has critical impact on system performance and energy consumption. To cope with complex dynamic behavior of applications, it is common to perform task mapping during runtime so that the utilization of processors and interconnect can be taken into account when deciding the allocation of each task. This paper has two major contributions, one of them targeting the general problem of evaluating dynamic mapping heuristics in NoC-based MPSoCs, and another focusing on the specific problem of finding a task mapping that optimizes energy consumption in those architectures.

Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration

As complexity of embedded system increases, configurable hardware is becoming more attractive because it provides a fast and efficient basis for design development. As a consequence, one of the most promising embedded architecture consists in the replication of Processing Elements (PEs) connected through a Network-on-Chip (NoC). Such architectures provide computation parallelism, scalability, and reduced design time thanks to reusability. This paper describes the development of a scalable, distributed memory, open source NoC-based platform called Open-Scale and its implementation into FPGA devices. The main objective of this platform is to provide a complete framework for research development on NoC-based distributed memory MPSoCs.

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

This paper introduces adaptive techniques targeted for heterogeneous manycore architectures and introduces the FlexTiles platform, which consists of general purpose processors with some dedicated accelerators. The different components are based on low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. These features enable a breakthrough in term of computing performance while improving the on-line adaptive capabilities brought from smart heuristics. Thus, we propose a virtualisation layer which provides a higher abstraction level to mask the underlying heterogeneity present in such architectures. Given the large variety of possible use cases that these platforms must support and the resulting workload variability, offline approaches are no longer sufficient because they do not allow coping with time changing workloads. The upcoming generation of applications include smart cameras, drones, and cognitive radio. In order to facilitate the architecture adaptation under different scenarios, we propose a programming model that considers both static and dynamic behaviors. This is associated with self adaptive strategies endowed by an operating system kernel that provides a set of functions that guarantee quality of service (QoS) by implementing runtime adaptive policies. Dynamic adaptation will be mainly used to reduce both overall power consumption and temperature and to ease the problem of decreasing yield and reliability that results from submicron CMOS scales.

Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip

This paper proposes a novel strategy for optimizing resources in Multi-Processor Systems-on-Chip (MPSoC). The approach is based on using control-loop feedback mechanism to maximize the efficiency on exploiting available resources such as CPU time, operating frequency, etc. Each Processing Element (PE) in the architecture is equipped with a frequency scaling module responsible for tuning the frequency of processors at run-time according to the application requirements. Results show the systems capability of adapting to disturbing conditions. For validation purposes we have implemented a multi-threaded MJPEG decoder together with an ADPCM audio decoder and a FIR.

Asynchronous parallel MPSoC simulation on the Single-Chip Cloud Computer

The growing complexity of embedded applications currently causes a trend towards multi-core processors in the embedded domain. Time-consuming detailed simulations make the design of such systems increasingly sophisticated. In this work, applicability of Parallel Discrete Event Simulation (PDES) in the context of cycle-accurate Multi-Processor System-on-Chip (MPSoC) simulation is investigated on the Single-chip Cloud Computer (SCC) from Intel. The presented strategy targets asynchronous parallel model execution where only adjacent model partitions need to synchronize with each other in order to advance in simulation time. Performance of the approach is evaluated by means of a scalable cycle-accurate MPSoC model called HeMPS. For a 8×8 RTL model measurements reveal a speedup versus sequential RTL simulation of 25.3×. When exchanging RTL processing elements by cycle-accurate simulators a speedup of 56.3× versus sequential RTL simulation is obtained. These results promise good suitability of the asynchronous strategy for detailed parallel MPSoC simulation on an architecture like the SCC.

Achieving composability in NoC-based MPSoCs through QoS management at software level

Multiprocessors systems on chip (MPSoCs) have become the de-facto standard in embedded systems. The use of Networks-on-chip (NoCs) provides to these platforms scalability and support for parallel transactions. The computational power of these architectures enables the simultaneous execution of several applications, with different time constraints. However, as the number of applications executing simultaneously increases, the performance of such applications may be affected due to resources sharing. To ensure applications requirements are met, mechanisms are necessary for ensuring proper isolation. Such a feature is referred to as composability. As the NoC is the main shared component in NoC-based MPSoCs, quality-of-service (QoS) mechanisms are mandatory to meet application requirements in term of communication. In this work, we propose a hardware/software approach to achieve applications composability by means of QoS management mechanisms at the software level. The conducted experiments show the efficiency of the proposed method in terms of throughput, latency and jitter for a real time application sharing communication resources with best-effort applications.

Modular Framework for Multi-level Multi-device MPSoC Simulation

Multi-Processor System-on-Chips (MPSoCs) as evolution of traditional embedded system architectures demand for a detailed exploration on architectures and system design. Simulation time and complexity are major issues, as such systems get more and more complex. This paper presents a novel simulation framework aiming the simulation of multiple MPSoC systems on different abstraction levels while using several simulation platforms concurrently in order to address aforementioned challenges. We introduce the concept of MultiX-Simulation which enables a tradeoff between performance and accuracy and allows for the flexible adaptation to various use cases. The backbone of the framework is formed by the High Level Architecture, a simulation middleware for Parallel Discrete Event Simulation. Also within this contribution different performance aspects of the framework are evaluated by using various multi-granular MPSoC system models.

A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC

The increasing failure rates observed in very deep sub micron silicon technologies pose a major problem to the design of future high-density SoCs. Emerging new architecture based on Multiprocessor SoC (MPSoC) gives the opportunity to exploit the natural redundancy with replicated spare processor in order to maintain the system performance in presence of failures. Based on the assumption that a transient loss of functionality can be tolerated, we study the feasibility and propose a cost-effective dependable hardware/software method which self-substitutes faulty processors with spare processors in a distributed manner. It guarantees the integrity, improves the availability and eases the maintainability of the MPSoC at system-level.