Gabriel Montoro López

Multi-dimensional LUT-based digital predistorter for concurrent dual-band envelope tracking power amplifier linearization

This paper presents a multi lookup table (LUT) implementation scheme for the 3D distributed memory polynomial (3D-DMP) behavioral model used in Digital Predistortion (DPD) linearization for concurrent dual-band envelope tracking (ET) power amplifiers (PAs). The proposed 3D-Distributed Memory LUTs (3D-DML) architecture is suitable for efficient FPGA implementation. In order to optimize the linearization performance as well as to reduce the number of resources of the 3D-DML model, a new variant of the Orthogonal Matching Pursuit (OMP) algorithm is proposed to properly select the best LUTs. Experimental results show that the proposed strategy reduces the number of LUTs (i.e. the number of coefficients) while meeting the targeted linearity levels.

Reducción de Factor de Cresta y Predistorsión Digital de Señales QAM de Banda Ancha para Equipos Backhaul de Próxima Generación

This paper evaluates the linearity performance in a wideband wireless backhaul transmitter when applying crest factor reduction (CFR) and digital predistortion (DPD) techniques to enhance the transmitted output power, and thus the power efficiency of the overall system, while fulfilling the communications system quality requirements and regulations.The CFR technique applied is the peak cancellation (PC), while the linearizer is based in an adaptive DPD with memory effects compensation. Order reduction techniques are also applied to mitigate the complexity of the DPD structure. The power amplifier is based in a 15 Watts GaN transistor. The test signal follows a multiband 4 channel 1024-QAM configuration (reaching up to 1 Gbps) with 12 dB of PAPR at RF and 112 MHz bandwidth (28 MHz each channel). A testbed for evaluating the PC and DPD linearization performance of the RF subsystem was deployed and experimental results are presented in this paper.