Gaku Nakagawa

Language runtime support for NVM/DRAM hybrid main memory

Replacing of DRAM in main memory with non-volatile memory (NVM) has several merits. However, NVM under development has some limitations in write operation. To overcome it, some previous researches proposed NVM/DRAM hybrid memory architecture. In the architecture, it needs to determine data placements between NVM and DRAM. In this paper, we advocate that programming language runtimes are useful for management of NVM/DRAM hybrid main memory. In addition, we will propose a method to manage NVM/DRAM hybrid main memory with language runtime support.

Preliminary Analysis of a Write Reduction Method for Non-volatile Main Memory on Jikes RVM

There are many researches and developments on byte accessible non-volatile memory (NVM). Byte accessible NVM can be used as not only storage but also main memory. Non-volatile main memory has two significant merits: reducing power consumption of main memory, flexible system standby and fast resume. However, NVM has bottlenecks in writing and limitation on the number of writing. To overcome this problem, there are some researches on hybrid memory architectures, which combine NVM and DRAM. On hybrid memory architectures, it needs to collect program characteristics of write access and allocate DRAM or NVM based on that characteristics. Previous works proposed to collect and allocate at hardware level or operating system level. At hardware or OS level, memory allocators can collect writing information of wide range of processes. However, they do not know contents of written data, thus they cannot allocate memory based on data characteristics. To solve this problem, we propose a method to obtain characteristics of writing and assign DRAM or NVM based on that information in previous work. The method applies write barrier of language runtimes to collect writing characteristics. This paper describes modification of our previous work and preliminary analysis for implementation the method on Jikes RVM.

NVM/DRAM hybrid memory management with language runtime support via MRW queue

Non-volatile memory (NVM), such as PCM, STTMRAM, and ReRAM, makes it possible to integrate secondary storage into main memory. This integration reduces I/O access times to typically slow block devices; however, it is unrealistic to construct a large capacity main memory with a single NVM at this time, because NVM have disadvantages regarding write access. Combining NVM and other memory devices is necessary to hide such disadvantages. In particular, we should place writehot data on DRAM and write-cold data on NVM. For data placement, programming language runtime supports are useful, since they have more detailed information about write access than the operating system. A previous study proposed a method to manage NVM/DRAM hybrid memory with programming language runtime supports, determining data placement based on the number of write accesses to each object (i.e., the individual counting method); however, this approach has two problems, namely memory efficiency and determination of threshold values for data placements. The Most Recent Write (MRW) queue method is an alternative method to distinguish between write-hot data and write-cold data. MRW queue manages the frequency of write accesses to objects. In this study, we discuss the problems of the individual counting method and show solutions using the MRW queue approach. Results of our experimentation show that the MRW queue method improves memory efficiency and reduces overhead of the individual counting method.

An Analysis of the Relationship between a Write Access Reduction Method for NVM/DRAM Hybrid Memory with Programming Language Runtime Support and Execution Policies of Garbage Collection

There are several research projects about new generation non-volatile memory (NVM), such as STT-MRAM, PCM and ReRAM. Non-volatile main memory makes it possible to integrate secondary storages in main memory. The integration enables to reduce I/O to slow block devices. It is, however, impossible to construct large capacity main memory with a single NVM in this point. It is required to combine DRAM and NVM or combine NVM and another NVM to construct unified non-volatile main memory. The previous researches discussed NVM/DRAM hybrid main memory architecture, which combine PCM and DRAM. In our previous work, we proposed a method to manage NVM/DRAM hybrid main memory with programming language runtimes supports. Language runtimes, such as Java runtimes, have more detailed informaion about write acceess to data than operating system has. The language runtime supports are useful to manage NVM/DRAM hybrid memory therefore. In the proposed method, the runtime migrates objects between NVM and DRAM based on the characteristics of write access. The language runtime executes the migration processes during garbage collection processes. The performance of the proposed method rely on the frequency of garbage collection. In this paper, we will discuss and do an experiment about how the frequency of garbage collection effects the performance of the proposed method. The results of the experiment shows that the improved method cut 91 percent of write access. The results also show that the improved method cut 50 percent of the usage of DRAM.

An architecture of operating system utilizing non-volatile main memory and heterogeneous multi-core

Reducing power consumption is a serious issue for todays computer systems. The measure to that issue, nonvolatile memory (NVM) and heterogeneous multicore architecture (HMA) draw attention. Non-volatile memory is the device that can maintain data without continuous power supply. This nonvolatile memory enable to reduce power consumption of main memory and zero-overhead hibernation. Heterogeneous multi-core architectures combine different cores. The cores are different each other in terms of instruction set architecture, circuit size and so on. Combination of various characteristics has significant possibility to achieve energy-efficient computer system. For the above reasons, combination of NVM and HMA enable to reduce power consumption of todays computer systems. Assuming using non volatile main memory, Operating System (OS) must be strict about memory management. Because, running time of OS go longer and risk of memory leaks get higher. In addition, code quality of OS must be high. To keep code quality, strong typing is useful. However C, which is mainstream of OS implementation, do not have mechanism avoid memory leak and strong typing mechanism. To solve this issue, there are some researches of implementing OS in Java have many case. However, previous works have certain performance problem. To solve this, we propose a new operating system architecture. This architecture aims that native machine code run as user programs while OS kernel is implemented in java. In this paper, we describe proposed architecture, explain a preliminary implementation of it, and show experiment by that implementation.

Behavior-Based Memory Resource Management for Container-Based Virtualization

Container-based virtualization is a virtualization technique at operating system level. It realizes a lightweight virtualization whose overhead is much less than hypervisor based virtualization. In a container, the programs often consume much more memory than the developer or the administrator expected. There are several methods to prevent such memory overuse. They, however, have each shortcoming such as its operation cost, the false-positive problem and so on. In this paper, we propose a new resource management method for container-based virtualization environment based on the resource consumption behavior. The method detects a wrong container that has a sign of memory overuse and makes a limitation to the detected container. A preliminary experiment for a proof-of-concept shows that it is possible to implement the proposed method in Linux kernel and it is effective to attack the problem situation.

Using DRAM as Cache for Non-Volatile Main Memory Swapping

The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years. However, these improvements have been seriously affecting power consumption. One of the greatest challenges is to achieve efficient power management for battery-equipped mobile devices. To solve this problem, the authors focus on the emerging non-volatile memory NVM, which has been receiving increasing attention in recent years. Since its performance is comparable with that of DRAM, it is possible to replace the main memory with NVM, thereby reducing power consumption. However, the price and capacity of NVM are problematic. Therefore, the authors provide a large memory space without performance degradation by combining NVM with other memory devices. In this study, they propose a design for non-volatile main memory systems that use DRAM as a swap space. This enables both high performance and energy efficient memory management through dynamic power management in NVM and DRAM.

Multi-level queue NVM/DRAM hybrid memory management with language runtime support

Non-volatile memory devices (NVM) devices, such as PCM, STT-MRAM, and ReRAM, enable the integration of secondary storage into main memory. This integration reduces I/O access to slow block devices; however, it is currently unrealistic to construct a large capacity main memory with a single NVM, because such devices have certain write access limitations. Combining NVM and other memory devices is necessary to overcome such disadvantages. Several researches discussed NVM/DRAM hybrid memory, combining NVM and DRAM. To use NVM/DRAM hybrid memory, the placement of data between NVM and DRAM must be determined. In particular, write-hot data should be allocated to DRAM and write-cold data to NVM. For data placement, programming language runtime supports are useful because they possess more detailed information about write access than the operating systems. A previous research proposed the individual counting method to manage NVM/DRAM hybrid memory with programming language runtime support that determine data placement based on the number of write accesses to each object. However, it is difficult to determine dynamically threshold values for data placements using the individual counting method. Here we propose a multi-level queue method to distinguish between write-hot and write-cold data. Experimental results show that the proposed method resolves the limitations of the individual counting method.

Modeling Energy Consumption of Memory Systems

The energy consumption of memory is one of the important metrics to evaluate memory systems. However, previous approaches such as using cycle accurate CPU and memory simulators require a long execution time for simulation. We are developing a model of energy consumption of DRAM-and NVM-based main memory, which allows estimating the energy consumption of a memory subsystem from easily observable performance metrics in real computer systems. In this paper, we conducted preliminary experiments using various types of workloads and observed the correlation of the memory throughput and energy consumption of DRAM. We used hardware performance counters to obtain memory throughput and energy consumption with minimum performance overhead.

Out of Memory Prevention Based on Memory Allocation Rate

The amount of free memory have a great influence on system stability because out of memory occurs performance degradation phenomena, unexpected process terminations and so on. Thus, It is an important administration task to design the memory utilization plan based on the characteristics of the processes. However, in sometimes, processes demand a large amount of main memory rapidly and unexpectedly due to various reasons (e.g. memory leaks, malicious programs, denial of service attacks to network servers). These unexpected large memory demands cause out of memory and make the systems unstable. Existing memory management mechanisms are somewhat effective to prevent such out of memory with the unexpected memory demands. However, the existing mechanisms have several problems arising from the difficulty in the discrimination between the expected and unexpected large memory demands. As a solution, we propose a new memory resource management method at the operating system level. The proposed method utilizes memory allocation rate to detect unexpected large memory demands, i.e., the operating system with the proposed methods regard the processes that demand memory rapidly as offending processes. In this paper, we will discuss the problem of existing memory management mechanism and describe the proposed method and show the evaluation experiments.