Ganesh C. Patil

A novel δ-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF applications

In this paper, a comparative analysis of single-gate dopant-segregated Schottky barrier (DSSB) SOI MOSFET and raised source/drain ultrathin-body SOI MOSFET (RSD UTB) has been carried out to explore the thermal efficiency, scalability and analog/RF performance of these devices. A novel p-type δ-doped partially insulated DSSB SOI MOSFET (DSSB Pi-OX-δ) has been proposed to reduce the self-heating effect and to improve the high-frequency performance of DSSB SOI MOSFET over RSD UTB. The improved analog/RF figures of merit such as transconductance, transconductance generation factor, unity-gain frequency, maximum oscillation frequency, short-circuit current gain and unilateral power gain in DSSB Pi-OX-δ MOSFET show the suitability of this device for analog/RF applications. The reduced drain-induced barrier lowering, subthreshold swing and parasitic capacitances also make this device highly scalable. By using mixed-mode simulation capability of MEDICI simulator a cascode amplifier has been implemented using all the structures (RSD UTB, DSSB SOI and DSSB Pi-OX-δ MOSFETs). The results of this implementation show that the gain-bandwidth product in the case of DSSB Pi-OX-δ MOSFET has improved by 50% as compared to RSD UTB and by 20% as compared to DSSB SOI MOSFET. The detailed fabrication flow of DSSB Pi-OX-δ MOSFET has been proposed which shows that with the bare minimum of steps the performance of DSSB SOI MOSFET can be improved significantly in comparison to RSD UTB.

Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits

In this paper, it has been shown that employing an underlap channel created by using the dual spacers in dopant-segregated Schottky barrier (DSSB) SOI MOSFET not only reduces the off-state leakage, short-channel effects and the parasitic overlap capacitances but also suppresses the variability induced by process fluctuations in the Schottky barrier height, dopant-segregation length and SOI film thickness of the device. However, the reduced effective gate voltage due to voltage drop across the underlap lengths also reduces the on-state drive current of the device. To alleviate this trade-off, a novel dual-k spacer underlap channel DSSB SOI structure has also been proposed in which the increased fringing electric field effect due to high-k inner spacer layer not only improves the on-state drive current but also reduces the off-state leakage current in both n-channel and p-channel devices. Despite the presence of high-k inner spacer layer increasing the fringing gate capacitance, the scalability in an optimized dual-k spacer underlap structure has improved by ∼60% and ∼35%, respectively over the conventional spacer overlap and underlap channel structures. In addition, the variability in an optimized dual-k spacer underlap structure has also been reduced by ∼50% and ∼30% respectively over the conventional spacer overlap and underlap channel structures. This clearly indicates that the proposed dual-k spacer underlap structure is a better choice for low-variability nanoscale CMOS logic circuits. The detailed fabrication flow of this novel device has also been proposed which demonstrates the use of conventional CMOS processes.

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

In this paper, the impact of segregation layer density (NDSL) and length (LDSL) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the NDSL the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the LDSL the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a commonsource amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing NDSL and LDSL of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits

A novel partially insulated Schottky source/drain MOSFET: Short channel and self heating effects

In this paper short channel and self heating effects in dopant segregated Schottky barrier (DSSB) silicon-on-insulator (SOI) MOSFET are investigated in sub-30 nm regime using two dimensional MEDICI simulator. In order to suppress these effects novel structures having dopant segregated Schottky source/drain (S/D) with buried oxide (BOX) only under S/D (DSSB Pi-OX) and DSSB Pi-OX with p-type delta doping in the oxide window formed under channel (DSSB Pi-OX-δ) have been proposed. The DSSB Pi-OX MOSFET is found better for reducing self heating effect but has worst short channel effects (SCE). On the other hand, DSSB Pi-OX-δ MOSFET not only reduces the self heating effect but also has SCE suppression better than DSSB SOI MOSFET. The extracted parasitic capacitances and S/D series resistance of DSSB SOI MOSFET and DSSB Pi-OX-δ MOSFET are found comparable to DSSB SOI MOSFET which shows that the performance advantages of DSSB SOI MOSFET are not affected with the proposed modification. The detailed fabrication flow of these novel devices is also proposed.

Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits

In this paper, asymmetric drain (ASD) under lap channel do pant-segregated Schottky barrier (DSSB) silicon-on-insulator (SOI) MOSFET has been proposed for low-power high performance (HP) CMOS circuits. The overlap channel at the source and under lap at the drain of this structure reduces the off-state leakage (IOFF), short-channel effects, gate induced drain leakage and improves the on-state drive current (ION) in comparison to symmetric source/drain (SSD) overlap and under lap structures. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and NOR gates based on these structures show that, although due to under lap at source/drain the reduced IOFF reduces the static power dissipation (Pstat) in SSD under lap based logic gates, the reduced ION due to voltage drop across the under lap lengths increases the propagation delay (tp) in these gates as compared to SSD overlap based CMOS gates. On the other hand, in the case of proposed ASD under lap the reduced IOFF with improved ION not only reduces Pstat but also reduces tp in comparison to SSD overlap and under lap based CMOS gates. Thus, the combined advantages of SSD under lap and overlap structures makes the proposed ASD under lap structure suitable for low-power HP CMOS logic circuits. The proposed fabrication flow of this novel device also demonstrates the use of conventional CMOS processes.

Asymmetric drain underlap dopant-segregated Schottky barrier ultrathin-body SOI MOSFET for low-power mixed-signal circuits

In this paper, asymmetric drain (ASD) underlap channel dopant-segregated Schottky barrier (DSSB) silicon-on-insulator (SOI) MOSFET has been proposed to improve the scalability and high-frequency performance of DSSB SOI MOSFET. The asymmetry of this device lies in the spacer thickness at the drain which creates an underlap channel with the same dopant-segregation length as that of the overlap channel at the source. The presence of overlap at the source and underlap at the drain of this device not only makes it immune to short-channel effects and the gate-induced drain leakage but also improves the analog figures of merit such as transconductance, intrinsic gain and unity-gain frequency of the device. In addition to this, the inverter power dissipation and the ring-oscillator delay in an optimized ASD underlap device are reduced by ∼40% and ∼20%, respectively, over the symmetric source/drain overlap and underlap channel devices. Thus, the significant improvement in both digital and analog figures of merit at nanoscale shows the suitability of the proposed device for low-power mixed-signal circuits. The proposed fabrication flow of this novel device is also similar to the DSSB SOI MOSFET flow and demonstrates the use of conventional CMOS processes.

Scalability and RF performance of nanoscale dopant segregated Schottky barrier SOI MOSFET

In this paper the effect of dopant segregation length (LDSL) on scalability and radio frequency (RF) performance of dopant segregated Schottky barrier (DSSB) silicon-on-insulator (SOI) MOSFET is investigated in sub-30nm regime using two dimensional MEDICI simulator. The range of LDSL used in this study is selected in such a way that both Gate — Source/Drain (G-S/D) underlap and G-S/D overlap structures can be analysed. It is found that DSSB SOI MOSFET with G-S/D underlap structure is highly scalable and fulfills the ION, IOFF and saturation threshold voltage (VTSAT) requirements of ITRS −2009 high performance (HP) logic technology nodes. However, the RF performance of this structure deteriorates significantly mainly because of reduction in transconductance (Gm). On the other hand the G-S/D overlap structure shows promising RF performance.

Si 3 N 4 : HfO 2 dual-k spacer dopant-segregated Schottky barrier SOI MOSFET for low-power applications

In this paper, it has been shown that employing an underlap channel in dopant-segregated Schottky barrier (DSSB) SOI MOSFET not only improves the scalability but also reduces the process induced threshold voltage variability of this device. However, the reduced effective gate voltage due to voltage drop across the underlap lengths also reduces the on-state drive current of the device. To alleviate this trade-off a novel Si3N4: HfO2 dual-k spacer underlap channel DSSB SOI MOSFET has also been proposed. Although the presence of HfO2 inner spacer layer increases the gate capacitance, the reduction in off-state leakage current and the improvement in on-state drive current over the conventional Si3N4: SiO2 spacer overlap/underlap channel DSSB SOI MOSFETs makes the proposed device suitable for low-power digital logic circuits.

Engineering buried oxide in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS circuits

Abstract In this paper CMOS logic circuit performance of dopant-segregated Schottky barrier (DSSB) SOI and δ-doped partially insulated DSSB SOI (DSSB Pi-OX-δ) MOSFETs has been explored by extensive mixed-mode device/circuit simulations. It has been found that, the presence of partial buried oxide and δ-doping in an n-channel and p-channel DSSB Pi-OX-δ MOSFETs not only suppresses the off-state leakage, short-channel effects, self-heating effect and the process induced threshold voltage variability but also improves the on-state drive current of the devices. Further, although switching energy in the CMOS inverter, NAND and NOR gates based on DSSB SOI and DSSB Pi-OX-δ MOSFETs is almost equal, static power dissipation and propagation delay in the logic gates based on DSSB Pi-OX-δ MOSFET are reduced by ∼75% and ∼20% respectively over the logic gates based on DSSB SOI device. Thus, employing partial buried oxide and δ-doping under the channel of DSSB SOI MOSFET not only eliminates the potential weaknesses of this device but also makes it a suitable candidate for nanoscale CMOS logic circuits.

UTBB with ground-plane dopant-segregated schottky barrier SOI MOSFET for thermally efficient low-variability nanoscale CMOS circuits

In this paper, a comparative study on self-heating effect, scalability, threshold voltage variability and CMOS logic performance of dopant-segregated Schottky barrier (DSSB) ultrathin body (UTB) thick buried oxide (BOX) and DSSB UTB thin BOX (UTBB) silicon-on-insulator (SOI) MOSFETs has been carried out by using the two dimensional MEDICI simulator. A novel DSSB UTBB-ground plane (GP) SOI MOSFET has also been proposed to improve the scalability and CMOS logic performance of DSSB SOI MOSFET. It has been found that, the presence of GP in DSSB UTBB-GP device not only improves the on-state drive current but also reduces the off-state leakage current of the device. Further, since the presence of GP cuts-off the path of the fringing field lines arising from the drain and the screening effect due to GP suppresses the random dopant fluctuations, both drain induced barrier lowering and threshold voltage variability in the proposed device are also low. In addition to this, the intrinsic gate delay and the static power dissipation in the case of DSSB UTBB-GP MOSFET are also reduced by ~80% and ~40% respectively over the DSSB thick BOX and DSSB UTBB SOI MOSFETs. Thus, significant reduction in self-heating effect, threshold voltage variability and the significant improvement in CMOS logic performance make the proposed device suitable for nanoscale CMOS logic circuits.