Gang Qu

Exposure in wireless Ad-Hoc sensor networks

Wireless ad-hoc sensor networks will provide one of the missing connections between the Internet and the physical world. One of the fundamental problems in sensor networks is the calculation of coverage. Exposure is directly related to coverage in that it is a measure of how well an object, moving on an arbitrary path, can be observed by the sensor network over a period of time. In addition to the informal definition, we formally define exposure and study its properties. We have developed an efficient and effective algorithm for exposure calculation in sensor networks, specifically for finding minimal exposure paths. The minimal exposure path provides valuable information about the worst case exposure-based coverage in sensor networks. The algorithm works for any given distribution of sensors, sensor and intensity models, and characteristics of the network. It provides an unbounded level of accuracy as a function of run time and storage. We provide an extensive collection of experimental results and study the scaling behavior of exposure and the proposed algorithm for its calculation.

Power optimization of variable voltage core-based systems

The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. We develop the design methodology for the low power core-based real-time system-on-chip based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which result in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the non-preemptive scheduling heuristic which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrial-strength multimedia and communication applications.

Synthesis techniques for low-power hard real-time systems on variable voltage processors

The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. We describe the synthesis of systems-on-a-chip based on core processors, while treating voltage (and correspondingly the clock frequency) as a variable to be scheduled along with the computation tasks during the static scheduling step. In addition to describing the complete synthesis design flow for these variable voltage systems, we focus on the problem of doing the voltage scheduling while taking into account the inherent limitation on the rates at which the voltage and clock frequency can be changed by the power supply controllers and clock generators. Taking these limits on rate of change into account is crucial, since changing the voltage by even a volt may take time equivalent to 100 s to 10000 s of instructions on modern processors. We present both an exact but impractical formulation of this scheduling problem as a set of nonlinear equations, as well as a heuristic approach based on reduction to an optimally solvable restricted ordered scheduling problem. Using various task mixes drawn from a set of nine real life applications, our results show that we are able to reduce power consumption to within 7% of the lower bound obtained by imposing no limit at the rate of change of voltage and clock frequencies.

Minimal and maximal exposure path algorithms for wireless embedded sensor networks

Sensor networks not only have the potential to change the way we use, interact with, and view computers, but also the way we use, interact with, and view the world around us. In order to maximize the effectiveness of sensor networks, one has to identify, examine, understand, and provide solutions for the fundamental problems related to wireless embedded sensor networks. We believe that one of such problems is to determine how well the sensor network monitors the instrumented area. These problems are usually classified as coverage problems. There already exist several methods that have been proposed to evaluate a sensor networks coverage.We start from one of such method and provide a new approach to complement it. The method of using the minimal exposure path to quantify coverage has been optimally solved using a numerical approximation approach. The minimal exposure path can be thought of as the worst-case coverage of a sensor network. Our first goal is to develop an efficient localized algorithm that enables a sensor network to determine its minimal exposure path. The theoretical highlight of this paper is the closed-form solution for minimal exposure in the presence of a single sensor. This solution is the basis for the new and significantly faster localized approximation algorithm that reduces the theoretical complexity of the previous algorithm. On the other hand, we introduce a new coverage problem - the maximal exposure path - which is in a sense the best-case coverage path for a sensor network. We prove that the maximal exposure path problem is NP-hard, and thus, we provide heuristics to generate approximate solutions.In addition, we demonstrate the effectiveness of our algorithms through several simulations. In the case of the minimal single-source minimal exposure path, we use variational calculus to determine exact solutions. For the case of maximal exposure, we use networks with varying numbers of sensors and exposure models.

Power optimization of variable-voltage core-based systems

The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. The energy efficiency of systems-on-a-chip (SOC) could be much improved if one were to vary the supply voltage dynamically at run time. We developed the design methodology for the low-power core-based real-time SOC based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which results in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrial strength multimedia and communication applications.

Exposure in wireless sensor networks: theory and practical solutions

Wireless ad hoc sensor networks have the potential to provide the missing interface between the physical world and the Internet, thus impacting a large number of users. This connection will enable computational treatments of the physical world in ways never before possible. In this far reaching scenario, Quality of Service can be expressed in terms of accuracy and/or latency of observing events and the overall state of the physical world. Consequently, one of the fundamental problems in sensor networks is the calculation of coverage, which can be defined as a measure of the ability to detect objects within a sensor filed. Exposure is directly related to coverage in that it is an integral measure of how well the sensor network can observe an object, moving on an arbitrary path, over a period of time. After elucidating the importance of exposure, we formally define exposure and study its properties. We have developed an efficient and effective algorithm for exposure calculations in sensor networks, specifically for finding minimal exposure paths. The minimal exposure path provides valuable information about the worst case exposure-based coverage in sensor networks. The algorithm can be applied to any given distribution of sensors, sensor and sensitivity models, and characteristics of the network. Furthermore, it provides an unbounded level of accuracy as a function of run time and storage. Finally, we provide an extensive collection of experimental results and study the scaling behavior of exposure and the proposed algorithm for its calculation.

Analysis of watermarking techniques for graph coloring problem

We lay out a theoretical framework to evaluate watermarking techniques for intellectual property protection (IPP). Based on this framework, we analyze two watermarking techniques for the graph coloring (GC) problem. Since credibility and overhead are the most important criteria for any efficient watermarking technique, we derive formulae that illustrate the trade-off between credibility and overhead. Asymptotically we prove that arbitrarily high credibility can be achieved with at most 1-color-overhead for both proposed watermarking techniques.

Effective iterative techniques for fingerprinting design IP

Fingerprinting is an approach that assigns a unique and invisible ID to each sold instance of the intellectual property (IP). One of the key advantages fingerprinting-based intellectual property protection (IPP) has over watermarking-based IPP is the enabling of tracing stolen hardware or software. Fingerprinting schemes have been widely and effectively used to achieve this goal; however, their application domain has been restricted only to static artifacts, such as image and audio, where distinct copies can be obtained easily. In this paper, we propose the first generic fingerprinting technique that can be applied to an arbitrary synthesis (optimization or decision) or compilation problem and, therefore to hardware and software IPs. The key problem with design IP fingerprinting is that there is a need to generate a large number of structurally unique but functionally and timing identical designs. To reduce the cost of generating such distinct copies, we apply iterative optimization in an incremental fashion to solve a fingerprinted instance. Therefore, we leverage on the optimization effort already spent in obtaining previous solutions, yet we generate a uniquely fingerprinted new solution. This generic approach is the basis for developing specific fingerprinting techniques for four important problems in VLSI CAD: partitioning, graph coloring, satisfiability, and standard-cell placement. We demonstrate the effectiveness of the new fingerprinting-based IPP techniques on a number of standard benchmarks.

Function-level power estimation methodology for microprocessors

We have developed a function-level power estimation methodology for predicting the power dissipation of embedded software. For a given microprocessor core, we empirically build the “power data bank”, which stores the power information of the built-in library functions and basic instructions. To estimate the average power of an embedded software on this core, we first get the execution information of the target software from program profiling/tracing tools. Then we evaluate the total energy consumption and execution time based on the “power data bank”, and take their ratio as the average power. High efficiency is achieved because no power simulator is used once the “power data bank” is built. We apply this method to a commercial microprocessor core and get power estimates with an average error of 3%. With this method, microprocessor vendors can provide users the “power data bank” without releasing details of the core to help users get early power estimates and eventually guide power optimization.

Temperature-aware cooperative ring oscillator PUF

Physical unclonable functions leverage the manufacture variations during silicon fabrication process and have found many security related applications. The ring oscillator PUF relies on pairs of ring oscillators which have sufficiently large difference in delay to generate reliable bits. Current RO PUF approaches use redundancy to provide reliability under different operating temperature and thus have very high hardware cost.We propose a temperature-aware cooperative (TAC) RO PUF implementation to reduce such cost. The basic idea is to allow a pair of ring oscillators to generate an unreliable bit as long as we can find means to convert it to a reliable bit. We define bit generation rules that explicitly take temperature into consideration and pair up the ring oscillator pairs so they can cooperate. Experiments on FPGA show that our approach can significantly improve the efficiency of the RO PUF implementation. With the same hardware that the current state-of-art approach requires to generate one reliable bit, our TAC RO PUF approach can generate as high as 1.8 reliable bits, that is, an 80% improvement in hardware utilization.