Gaobo Xu

Study on characteristics of thermally stable HfLaON gate dielectric with TaN metal gate

We have fabricated the thinnest equivalent oxide thickness of 0.62 nm HfLaON gate dielectric for TaN/HfLaON/SiOx gate stack with improved thermal stability and electrical characteristics. The HfLaON film was deposited using reactive sputtering of Hf–La and Hf targets by alternate means in N2/Ar ambience. The effects of different postdeposition annealing conditions and various La contents on the properties of HfLaON film and its interface have been investigated; the corresponding mechanisms are discussed. The gate tunneling leakage is five orders of magnitude lower than the normal polycrystalline silicon/SiO2 structure. The effective work function with TaN metal gate is 4.06 eV.

Gallium-Incorporated TiN Metal Gate With Band-Edge Work Function and Excellent Thermal Stability for PMOS Device Applications

A cost-effective method for modulating the effective work function (EWF) of a metal gate while simultaneously decreasing the equivalent oxide thickness (EOT) of a high-k dielectric is proposed for the first time. By incorporating gallium (Ga) into the TiN/HfLaON/interfacial layer (IL) SiO2 PMOS gate stack, a band-edge EWF of 5.18 eV and an EOT of 0.57 nm can be obtained. Excellent thermal stability was maintained even after the post metal anneal (PMA) at 1000°C. The impacts of TiN thickness, Ga implant doses, and PMA conditions on the properties of the Ga-incorporated TiN/HLaON/IL SiO2 gate stack are investigated, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the gate-first process flow to fabricate PMOSFETs with a minimum gate length of 28 nm.

FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin

The large parasitic resistance has become a critical limiting factor to on current (ION) of FinFET and nanowire devices. Fully metallic source and drain (MSD) process is one of the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD process on fin-on-insulator (FOI) FinFET is investigated extensively for the first time. By forming fully Ni(Pt) silicide on physically isolated fins, about 90% reduction in contacted resistivities (Rcs) and 55% reduction in sheet resistances (Rss) are achieved without obvious junction leakage degradation. As a consequence, Ion of transistor, with gate length (Lg) of 20nm, is increased 30 times, up to 547μA/μm for NMOS and 324 μA/μm for PMOS, respectively. Excellent controls of SCE and channel leakage with 47% DIBL, 32% SS and 2.5% device leakages reductions over the counterpart of conventional bulk FinFETs are also obtained. Meanwhile, the fully MSD process induces clear tensile stress into narrow fin-channel, resulting in enhanced electron mobility in NMOS. A further improvement in PMOS drive ability (486μA/μm) by using Schottky barrier source and drain (SBSD) technology is also explored.

Ion-Implanted TiN Metal Gate With Dual Band-Edge Work Function and Excellent Reliability for Advanced CMOS Device Applications

This paper proposed, for the first time, that the dual band-edge effective work functions are achieved by employing a single metal gate (MG) and single high-k (HK) dielectric via ion implantation into a TiN MG for HP CMOS device applications under a gate-last process flow. The P/BF2 ion-implanted TiN/HfO2/ILSiO2 gate-stack does not degrade the gate leakage, reliability, and carrier mobility, and reduces the effective oxide thickness. The impact of P/BF2 ion implant energy, dose, and TiN gate thickness on the properties of implanted TiN/HfO2/ILSiO2 gate-stack is studied, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the replacement MG and HK/MG last process flow to fabricate HP CMOSFETs and CMOS 32 frequency dividers with a minimum gate length of 25 nm.

Investigation of Key Technologies for Poly-Si/TaN/HfLaON/IL

We demonstrated for the first time integration of a poly-Si/TaN/HfLaON/IL SiO₂ gate-stacks into high-performance sub-30-nm nMOSFETs using a gate-first process flow successfully. The properties of TaN/HfLaON/IL SiO₂ gate-stacks were studied. The results showed that the HfLaON gate dielectric material exhibited excellent thermal stability and electrical characteristics. A three-step dry etching method used to etch poly-Si/TaN/HfLaON/IL SiO₂ gate-stack was proposed to provide an effective pathway for patterning the complex gate-stacks. At V_DS=V_GS=0.9 V, the drive current I_ON of 410 μA/μm was achieved at an OFF-state leakage current I_OFF of 180 nA/μm. The threshold voltage of saturation extracted at I_DS of 3 μA/μm was 0.14 V. The subthreshold slope of 92 mV/decade and drain induced barrier lowering of 93 mV/V were obtained.

{\rm SiO}_{2}

HfSiON gate dielectric with equivalent oxide thickness of 10Å was prepared by reactive sputtering. It exhibits good physical and electrical characteristics, including good thermal stability up to 900°C, high dielectric constant and low gate leakage current. It was integrated with TaN metal gate in a novel gate-last process flow to fabricate NMOSFET. In the process, poly-silicon was deposited on HfSiON gate dielectric as dummy gate and replaced by TaN metal gate after source/drain formation. Because of the metal gate formation after the ion-implant doping activation at high temperature, HfSiON/TaN NMOSFET with good driving ability and excellent sub-threshold characteristics was fabricated.

Gate-Stacks in Advanced Device Applications

Dramatic EOT shrinking and Vfb increasing were observed when implanting Ga ions into high-k/metal-gate stack. Experiments with different gate-metal thickness, dosages, ion types, and post gate-etch anneal conditions were studied. Elastic dipole theory, for the first time, is proposed and ab-initio simulations were conducted to explain the unexpected trends. This theory offers a good guide to choose plug-in materials for high-k/metal-gate optimization.