Gaofeng Lv

Towards Spoofing Prevention Based on Hierarchical Coordination Model

A novel approach for filtering spoofed IP packets, called spoofing prevention based on hierarchical coordination model, is proposed. In the approach a unique temporal signature is associated with each ordered pair of source destination networks. Each packet leaving a source network S is marked with the signature Sig(S,D) , associated with (S,D) , where D is the destination network. Upon arrival at the destination network the signature is verified and removed. The method verifies the authenticity of packets carrying the address s which belongs to the source address space of network S indexed by the signature. While the information about source address spaces of network is transmitted by hierarchical coordination model, in which by the same method the information is propagated and processed for routers residing in the same hierarchical, furthermore using dynamic bloom filter the information is fused to be delivered over hierarchies, thus the implementation is efficient The major benefits of SP-HCM are the strong incentive it provides to network operators to implement it, and the fact that the approach lends itself to stepwise deployment, since it benefits networks deploying the approach even if it is implemented only on parts of the Internet.

FRINGE: Improving the scalability of Ethernet DCN via efficient software-defined edge control

This paper introduces a topology-independent software-defined edge control framework named FRINGE to scale out the Ethernet Datacenter Network (DCN). FRINGE exploits programmable OpenFlow-enabled switches deployed at the edge of DCN to aggregate the forwarding rules without introducing extra packet headers. We implement the proposed FRINGE framework in an SDN prototyping environment and validate it under three typical DCN topologies including Multi-Root Tree, HyperX and Jellyfish, where three different types of DCN workloads are applied. Evaluation results reveal that FRINGE can significantly reduce the total number of rules in all network devices and suppress most of the useless broadcast packets in the DCN.

DEFIO: A Software Defined Storage Network Architecture in HPC Environments

High performance computing (HPC) has witnessed a great boom of computing capability in recent years, however storage capacity fails to keep pace with that rapid growth, coun-teracting the benefits brought by higher computing power. Two dominating bottlenecks have been pointed out: firstly, Small-size IO requests fail to leverage the advantage of current distributed file systems and non-contiguous I/O access pattern induces more movement of disk heads. Secondly, coexistence of multi-tenant applications makes bandwidth guarantee more urgent while unfortunately, more complex. This article proposes a software defined storage network in HPC environments called DEFIO, providing a solution to reduce the adverse effect imposed by the above two bottlenecks, under the proposed architecture we estab-lish several key technologies to solve performance and scalability issues in HPC storage networks.

Demostration of Self-Described Buffer for Accelerating Packet Forwarding on Multi-core Servers

Network processing platform based on the multi-core CPU becomes more and more prevailing in nowadays. Buffer allocation/deallocation operations consume a large number of CPU cycles in packet I/O process. The problem becomes even worse in the scenario of packet forwarding, as buffer allocation/deallocation operations are more frequent than the host-based network applications. We thus propose a novel data structure for packet buffer management on multi-cores, named Self-Described Buffer (SDB), which merges the separated descriptor and metadata into packet buffer. SDB management overhead can be greatly reduced by utilizing the compact data structure, and zero-overhead buffer management can be further achieved by offloading SDB allocation/deallocation operations to NIC. We have prototyped SDB enabled NIC, named BcNIC, on NetFPGA-10G. In the demo, we will illustrate the advantages of the SDB scheme by comparing the performance of BcNIC with the traditional NIC on multi-core platforms.

Towards Internet Innovation: Software Defined Data Plane

In order to support new network architectures, Openflow implements flows forwarding based on multiple tables via pipelines, which increases the difficulty of the implementation. With the advent of multi-core CPU, a software defined data plane, LabelCast, is proposed, which characterizes the ability of forwarding operations and processing services through the Label table and Cast table. Forwarding layer lookups based on fixed-length labels and schedules packets processing, including light-semantics action instructions of general process, which is easy to be realized and is denoted by the Label table, and protocol semantics or status-related service of special process, which could be enriched via opening resources within network devices and is arranged by the Cast table. LabelCast supplies a reliable and programmable data plane, and could load multiple network architectures, so as to facilitate Internet innovation.

An Efficient Policy-based Packet Scheduler With Flow Cache

To meet the requirements of parallelism, flexibility and extensibility, the multi-processor elements (PEs) architecture is widely applied in modern network processors (NPs) to support high-speed links of 10 Gbps. Multi-PEs are often organized in parallel to achieve efficient packet forwarding. Its a challenge to schedule the incoming packets from high-speed links to be processed by multiple PEs in parallel. In this paper, we propose policy-based packet scheduler employing flow cache for 10 Gbps NPs. For TCP flows, PPS-FC employs a flow cache, records the mapping relationship between TCP flow bundles and PEs and rates of flow bundles and utilizes the characteristic of flow timeout to design the scheme of cache management Meanwhile, according to the load-balancing indicator sigma(t) the scheduler shifts the high-rate flow bundles of the heavy-loaded PE to the light-loaded PE to preserve load balancing. The effectiveness of the scheduler with the well-chosen design parameters is evaluated by simulation with extrapolated workloads.

HiTrans: An FPGA-Based Gateway Design and Implementation in HPC Environments

Infiniband and 10i?źGbps Ethernet are two main high speed interconnect technologies adopted by High Performance Computing Environment, Ethernet is currently pervasively leveraged by storage devices while Infiniband is commonly used for high speed transmission among compute nodes, this distinction introduces interoperation between two heterogeneous networks which necessitate gateways, traditional software-based storage gateways show shortcomings in terms of high CPU utilization, long processing latency and poor performance, ASIC-based gateways overcome the above drawback but do not own enough programmability which enables flexible operations. This paper designs and implements an FPGA-based storage gateway called HiTrans to connect Infiniband and Ethernet in HPC environments based on EoIB technology, our main contributions focus on proposing the core processing procedure of HiTrans, and a static address mapping algorithm supporting fast protocol conversion between heterogeneous networks which boosts packet processing capability of storage gateway and reduces storage I/O latency. Experiment result has shown that performance of Hi-Trans can reach line-rate forwarding from Infiniband to Ethernet which is 3 times higher than traditional software-based implementation.

Topology-independent Software-Defined Edge Control for Scalable Ethernet DCN

Although Layer-2 networking meets the requirement of data center operators, it can not scale in the existing Ethernet Data center Network (DCN). In this paper, motivated by the backwards compatibility of OpenFlow with current commodity switches, we propose a topology-independent software-defined edge control framework, named FRINGE, which exploits the scalable capability for Ethernet DCN. FRINGE is able to leverage programmable OpenFlow switches deployed at the edge of DCN to intercept broadcast packets and achieve address aggregation through switch-based MAC address resolution. We implement the proposed framework in an SDN prototyping environment and validate it under typical DCN fabrics, where different types of workloads are applied. Evaluation results reveal that FRINGE is able to significantly reduce the total number of rules in all network devices, suppress broadcast packets and exploit redundant paths, which improves the scalability of Ethernet DCNs.

Neighbor Gradient-based Multicast Routing for Service-Oriented Applications

With the prevalence of diverse services-oriented applications, such as IPTV systems and on-line games, the current underlying communication networks face more and more challenges on the aspects of flexibility and adaptability. Therefore, an effective and efficient multicast routing mechanism, which can fulfill different requirements of different personalized services, is critical and significant. In this paper, we first define the neighbor gradient, which is calculated based on the weighted sum of attributes such as residual link capacity, normalized hop count, etc. Then two distributed multicast routing algorithms which are neighbor Gradient-based Multicast Routing for Static multicast membership (GMR-S) and neighbor Gradient-based Multicast Routing for Dynamic multicast membership (GMR-D), are proposed. GMR-S is suitable for static membership situation, while GMR-D can be used for the dynamic membership network environment. Experimental results demonstrate the effectiveness and efficiency of our proposed methods.