Gareth Lee

REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems

The feature of partial reconfiguration provided by currently available field programmable gate arrays (FPGAs) makes it possible to change hardware modules while others keep working. The combination of this feature and the high gate capacity enables the integration of dynamic systems that can be adapted to changing demands during runtime. Placing the dynamically changing modules along a horizontal communication infrastructure does not only provide communication facilities it also enables the relocation of pre-synthesized modules by bitstream manipulations. The exact placement of an incoming module is determined according to the current resource allocation, which results in an online placement problem. In order to prevent any extra configuration overhead for the relocation process, we developed the REPLICA (relocation per online configuration alteration) filter, which is capable of performing the necessary bitstream manipulations during the regular download process. The filter architecture, a configuration manager and an evaluation example are presented in this paper.

Software component certification

Although the stringent requirements of some critical applications may require independent certification, the authors see software developer self-certification as a viable alternative in many other cases. They accept that using software certification laboratories (SCLs) may work well for certain software distribution models, but they cannot be applied to all types of software development. The approach has several drawbacks. For example, an SCL may work well for larger software houses that ship mass-marketed software applications to the public, but it is less satisfactory for smaller developers who make reusable components or safety-critical software or for developers who belong to the freeware community.

Australian sign language recognition

This paper presents an automatic Australian sign language (Auslan) recognition system, which tracks multiple target objects (the face and hands) throughout an image sequence and extracts features for the recognition of sign phrases. Tracking is performed using correspondences of simple geometrical features between the target objects within the current and the previous frames. In signing, the face and a hand of a signer often overlap, thus the system needs to segment these for the purpose of feature extraction. Our system deals with the occlusion of the face and a hand by detecting the contour of the foreground moving object using a combination of motion cues and the snake algorithm. To represent signs, features that are invariant to scaling, 2D rotations and signing speed are used for recognition. The features represent the relative geometrical positioning and shapes of the target objects, as well as their directions of motion. These are used to recognise Auslan phrases using Hidden Markov Models. Experiments were conducted using 163 test sign phrases with varying grammatical formations. Using a known grammar, the system achieved over 97% recognition rate on a sentence level and 99% success rate at a word level.

A software component verification tool

Component based software engineering depends on reliable, robust components, since it may omit a unit test phase wholly or partially from the development cycle. The paper describes a tool that allows a component developer to design and run verification tests. In developing components for our library, we found it necessary to provide multiple mechanisms for identifying and capturing tests to overcome the limitations of any single mechanism. Once specified, test specifications and test results are stored in XML documents, providing a standard, portable form of storing, retrieving and updating test histories. One module of our component test bench, the test pattern verifier, has been designed to be general, lightweight and portable, so that it can be packaged with a component and its test specifications. This allows a component user to verify a components compliance with specifications in a target environment.

Using Symbolic Execution to Guide Test Generation

Although a number of weaknesses of symbolic execution, when used for software testing, have been highlighted in the literature, the recent resurgence of strongly‐typed languages has created opportunities for re‐examining symbolic execution to determine whether these shortfalls can be overcome. This paper discusses symbolic execution in general and makes two contributions: (a) overcoming one of the key problems, analysing programs with indexed arrays; and (b) describing the incorporation of a symbolic execution module for test case generation into an integrated testing tool. For methods which index arrays, a new approach determines all the possible values of each array index, allowing the generation of equivalence classes for every possible combination of array element aliases. An incremental simplification approach, which converts path expressions to canonical forms in order to identify infeasible paths at the earliest opportunity and thus reduce the analysis time, is also described. Symbolic execution is most effective when included in an integrated test and analysis environment: a component test bench was built with a symbolic execution module integrated into it, providing a toolbox of software component test and code analysis methods aimed at programmers at all levels. Copyright

Real-Time Three Dimensional Vision

Active systems for collision avoidance in ‘noisy’ environments such as traffic which contain large numbers of moving objects will be subject to considerable interference when the majority of the moving objects are equipped with common avoidance systems. Thus passive systems, which require only input from the environment, are the best candidates for this task. In this paper, we investigate the feasibility of real-time stereo vision for collision avoidance systems. Software simulations have determined that sum-of-absolute-difference correlation techniques match well but hardware accelerators are necessary to generate depth maps at camera frame rates. Regular structures, linear data flow and abundant parallelism make correlation algorithms good candidates for reconfigurable hardware. The SAD cost function requires only adders and comparators for which modern FPGAs provide good support. However accurate depth maps require large disparity ranges and high resolution images and fitting a full correlator on a single FPGA becomes a challenge. We implemented SAD algorithms in VHDL and synthesized them to determine resource requirements and performance. Altering the shape of the correlation window to reduce its height compared to its width reduces storage requirements with negligible effects on matching accuracy. Models which used the internal block memory provided by modern FPGAs to store the ‘inactive’ portions of scan lines were compared with simpler models which used the logic cell flip-flops. From these results, we have developed a simple predictor which enables one to rapidly determine whether a target appliction is feasible.

Automatic Recognition of Colloquial Australian Sign Language

This paper presents an automatic Australian sign language (Auslan) recognition system, which tracks multiple target objects (the face and hands) throughout an image sequence and extracts features for the recognition of sign phrases. Tracking is performed using correspondences of simple geometrical features between the target objects within the current and the previous frames. In signing, the face and a hand of a signer often overlap, thus the system needs to segment these for the purpose of feature extraction. Our system deals with the occlusion of the face and a hand by detecting the contour of the foreground moving object using a combination of motion cues and the snake algorithm. To represent signs, features that are invariant to scaling, 2D rotations, and signing speed are used for recognition. The features represent the relative geometrical positioning and shapes of the target objects, as well as their directions of motion. These are used to recognise Auslan phrases using Hidden Markov Models. Experiments were conducted using 163 test sign phrases with varying grammatical formations. Using a known grammar, the system achieved over 97% recognition rate on a sentence level and 99% success rate at a word level.

Study on column wise design compaction for reconfigurable systems

Some of currently available field programmable gate arrays (FPGAs) can be reconfigured partially, which makes it possible to build up dynamic systems that can be adapted to changing demands during runtime. One basic aspect of such a system is the way the dynamic hardware modules are placed on the FPGA. As most FPGAs offer partial reconfiguration in a column wise manner, a 1D placement of column wise implemented modules seems to be promising. Within This work we present a design study that determines the effects of a column wise module implementation on the resulting frequency and power consumption.

A generalised spreadsheet verification methodology

Although spreadsheets have been around for over thirty years, we are only just realising their importance. Most companies use spreadsheets in their decision-making processes, but rarely employ any form of testing. This paper shows how an all-uses test adequacy technique can be integrated into Microsofts Excel. The modular technique adopted makes the implementation spreadsheet package independent. It also includes a user interface, to assist developers specify test cases and a technique for recording test cases and session information. In particular it presents a systematic technique for constructing test cases. As a key problem with spreadsheet development is the inexperience of developers, this paper describes an easy to use tool that will improve the standard of spreadsheets developed.

Dataflow Java: implicitly parallel Java

Dataflow computation models enable simpler and more efficient management of the memory hierarchy-a key barrier to the performance of many parallel programs. This paper describes a dataflow language based on Java. Use of the dataflow model enables a programmer to generate parallel programs without explicit directions for message passing, work allocation and synchronisation. A small handful of additional syntactic constructs are required. A pre-processor is used to convert Dataflow Java programs to standard portable Java. The underlying run-time system was easy to implement using Javas object modelling and communications primitives. Although raw performance lags behind an equivalent C-based system, we were able to demonstrate useful speedups in a heterogeneous environment, thus amply illustrating the potential power of the Dataflow Java approach to use all machines-of whatever type-that might be available on a network when Java JIT compiler technology matures.