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Featured researches published by Gary A. Gibson.


international symposium on microarchitecture | 1991

The Metaflow architecture

Val Popescu; Merle A. Schultz; John E. Spracklen; Gary A. Gibson; Bruce D. Lightner; David Isaman

The Metaflow architecture, a unified approach to maximizing the performance of superscalar microprocessors, is introduced. The Metaflow architecture exploits inherent instruction-level parallelism in conventional sequential programs by hardware means, without relying on optimizing compilers. It is based on a unified structure, the DRIS (deferred-scheduling, register-renaming instruction shelf), that manages out-of-order execution and most of the attendant problems. Coupling the DRIS with a speculative-execution mechanism that avoids conditional branch stalls results in performance limited only be inherent instruction-level parallelism and available execution resources. Although presented in the context of superscalar machines, the technique is equally applicable to a superpipelined implementation. Lightning, the first implementation of the Metaflow architecture, which executes the Sparc RISC instruction set is described.<<ETX>>


Archive | 1990

Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched

Valeri Popescu; Merle A. Schultz; Gary A. Gibson; John E. Spracklen; Bruce D. Lightner


Archive | 1995

Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code

Valeri Popescu; Merle A. Schultz; Gary A. Gibson; John E. Spracklen; Bruce D. Lightner


Archive | 1995

Processor architecture supporting multiple speculative branching

Valeri Popescu; Merle A. Schultz; Gary A. Gibson; John E. Spracklen; Bruce D. Lightner


Archive | 2011

Fine grain performance resource management of computer systems

Gary A. Gibson; Valeri Popescu


Archive | 1995

Processor architecture providing out-of-order execution

Valeri Popescu; Merle A. Schultz; Gary A. Gibson; John E. Spracklen; Bruce D. Lightner


Archive | 1995

Processor architecture supporting multiple speculative branches and trap handling

Valeri Popescu; Merle A. Schultz; Gary A. Gibson; John E. Spracklen; Bruce D. Lightner


Archive | 1996

Processor architecture providing speculative, out of order execution of instructions

Valeri Popescu; Merle A. Schultz; Gary A. Gibson; John E. Spracklen; Bruce D. Lightner


Archive | 1997

Processor architecture providing speculative, out of order execution of instructions and trap handling

Valeri Popescu; Merle A. Schultz; Gary A. Gibson; John E. Spracklen; Bruce D. Lightner


Archive | 2011

Control of processor cache memory occupancy

Gary A. Gibson; Valeri Popescu

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