Gary D. Grise

At-Speed Structural Test For High-Performance ASICs

At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach

Low cost at-speed testing using On-Product Clock Generation compatible with test compression

At-speed testing with functional speed clocks is often done using On-Product Clock Generation (OPCG). When test compression logic is also embedded within the circuits DFT architecture, the loading of the OPCG programming bits can impact test compression results. We present an approach to the use of OPCG that enables high-speed testing and is compatible with test compression. It also enables the use of tests that pulse multiple domains to further reduce test time and data volume. It also supports generation of inter-domain and static ATPG tests. We present results on four designs; one design shows an over 35% reduction in patterns due to use of multiple clock domains per test. An additional 10+% savings is possible using side-scan to load the OPCG programming registers.

A flexible and scalable methodology for GHz-speed structural test

At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Simulation-based functional test is difficult because low-cost testers are unable to supply multiple asynchronous clocks to the IC. Moreover, low-cost testers simply cannot operate at chip speed. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for GHz-speed structural test of ASICs having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We also describe a method to test asynchronous clock domains simultaneously. Experimental results for two multi-million gate ASICs demonstrate high at-speed coverage

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation

Although on-product clock generation (OPCG) has been used for many years, often in conjunction with logic and memory BIST, it has usually been a very manual process to identify the cut-points and the OPCG behavior to ATPG tools so they can avoid dealing directly with the OPCG logic. To support programmable OPCG logic in an ASIC methodology flow required us to find a way to automate the handling of the OPCG logic and the various clocking sequences it can produce. This paper describes how we provide a means for dealing with the programmable aspects of OPCG for use during ATPG and shows some results.

An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs

In contract manufacturing, the circuit netlist is owned by the ASIC customer. The manufacturer is required to work strictly within the design structure established by the customer. To manufacture high-quality components in this environment, it is critical to meet the customers mandated quality and performance criteria, while minimizing hardware overhead and introducing little or no design change. In this paper, the authors present a test framework for contract-manufactured ASICs using low-cost testers. Key aspects of the framework are low hardware overhead, significant savings in test data volume and test cost, and tight integration of the at-speed and ATE-driven test components to the design and manufacturing process.

Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs

Performance verification is critical to high-performance ASICs manufacturing. Performance verification ensures that only those chips whose performance is higher than an advertised threshold are shipped to demanding customers. This provides a means to weed out nominal performance ASICs, and also ship ASICs at difference grades. At-speed structural test can provide performance verification capability at very low cost. In this paper, we present a scalable and flexible structural test method for performance verification of ASICs. The proposed method requires no tight restrictions on the circuit design. Moreover, low-cost testers are used, thus sharply reducing test cost

Performance verification of high-performance ASICs using at-speed structural test

Performance verification is becoming critical to high performance ASICs manufacturing. Performance verification ensures that only those ASICs whose performance is higher than an advertized threshold are shipped to demanding customers. This provides a means to weed out nominal performance ASICs, and also ship ASICs at difference grades. However, performance verification based on functional test requires high-functionality testers that can supply multiple asynchronous clocks. Additionally, functional test requires expensive testers that can operate at the speed of the fastest clock domain on the ASIC. As an alternative, at-speed structural test can provide performance verification capability at very low cost. However, existing structural test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a scalable and flexible structural test method for performance verification of GH-speed ASICs. The proposed method requires no tight restrictions on the circuit design. Moreover, low-cost testers are used, thus sharply reducing test cost.