Gary E. Herman

The datacycle architecture for very high throughput database systems

The evolutionary trend toward a database-driven public communications network has motivated research into database architectures capable of executing thousands of transactions per second. In this paper we introduce the Datacycle architecture, an attempt to exploit the enormous transmission bandwidth of optical systems to permit the implementation of high throughput multiprocessor database systems. The architecture has the potential for unlimited query throughput, simplified data management, rapid execution of complex queries, and efficient concurrency control. We describe the logical operation of the architecture and discuss implementation issues in the context of a prototype system currently under construction.

VLSI accelerators for large database systems

An experimental VLSI accelerator research prototype designed and fabricated for relational data filtering is described. It performs high-speed associative search and aggregation operations for formatted databases. For unformatted databases, an experimental fast string search VLSI accelerator that provides a few orders-of-magnitude improvement in text search speed has been developed. The VLSI accelerators have precise instruction sets and hardware interfaces that facilitate their integration into general-purpose computer systems and dedicated systems. Application of the accelerators to both general-purpose and dedicated computer systems is discussed. Related work is examined.<<ETX>>

A rapid turnaround design of a high speed VLSI search processor

Performance of relational database systems is a major impediment to their use in many applications. We have designed and implemented a customized RISC processor to accelerate associative search and aggregation operations for relational database systems. Since the processor is programmable and supports many queries concurrently, a system utilizing tens of such processors is capable of handling thousands of complex search requests simultaneously. While the design of a VLSI programmable processor is a complex process, research prototyping requires a fast turnaround design process. We took advantage of the logic programming paradigm and the silicon compiler technology to explore and simulate architecture alternatives prior to the actual implementation. The prototyping process allowed us to complete the chip design in nine months. The resulting processor, fabricated in 2 Itm CMOS technology, consists of 91,000 transistors, executes over 18 million predicate evaluations per second, and searches database contents at 74 megabytes per second.

The Case for Orderly Sharing

Transaction processing systems with the functionality and throughput desirable to support future telecommunications network applications appear to be beyond the capability of conventional multiprocessor architectures. A central obstacle to realizing such systems is the cost of coordinating access of transactions in the various processors to shared data. In this paper, we introduce the principle of orderly sharing — the efficient coordination of many loosely coupled processing elements acting on shared resources (e.g., data items) through orderly distribution of information regarding the state of resources throughout the system. We illustrate the application of this principle in the context of a novel system called the Datacycle architecture [Herm87a].

Achieving throughput and functionality in a common architecture: the Datacycle experiment

Summary form only given. The Datacycle database architecture is based on repetitive broadcast of database contents over high bandwidth channels and on-the-fly filtering of database contents to extract records of interest. These two mechanisms-high speed broadcast and on-the-fly filtering-result in a system that achieves the goals of high performance transaction processing, a powerful and flexible query capability, and high levels of concurrent access to a single database by multiple applications. The prototype system comprises multiple pump boards, each of which stores up to 128 Mbytes of database contents, and multiple access manager boards, each of which contains three on-board VLSI data filter chips. Each VLSI filter executes queries against the contents of a 53 Mbyte/second broadcast channel; selected records and/or computed aggregate values are returned to the host application.<<ETX>>

The Datacycle architecture and research prototype

Research on the Datacycle architecture attempts to achieve, in a single architecture, the goals of high performance transaction processing, a powerful and flexible query capability, and high levels of concurrent access to a single database by multiple applications. The Datacycle architecture meets these goals by providing independent structuring and scaling of processing resources, both for processing individual queries (intra-query parallelism) and for overall throughput (inter-transaction parallelism). This paper describes the experimental Datacycle research prototype implemented at Bellcore. Building the prototype forced us to identify and overcome a number of key engineering and implementation issues and provides a better understanding of the value of this approach to database architecture.<<ETX>>