Gary S. Tyson

iFall: An android application for fall monitoring and response

Injuries due to falls are among the leading causes of hospitalization in elderly persons, often resulting in a rapid decline in quality of life or death. Rapid response can improve the patients outcome, but this is often lacking when the injured person lives alone and the nature of the injury complicates calling for help. This paper presents an alert system for fall detection using common commercially available electronic devices to both detect the fall and alert authorities. We use an Android-based smart phone with an integrated tri-axial accelerometer. Data from the accelerometer is evaluated with several threshold based algorithms and position data to determine a fall. The threshold is adaptive based on user provided parameters such as: height, weight, and level of activity. The algorithm adapts to unique movements that a phone experiences as opposed to similar systems which require users to mount accelerometers to their chest or trunk. If a fall is suspected a notification is raised requiring the user’s response. If the user does not respond, the system alerts pre-specified social contacts with an informational message via SMS. If a contact responds the system commits an audible notification, automatically connects, and enables the speakerphone. If a social contact confirms a fall, an appropriate emergency service is alerted. Our system provides a realizable, cost effective solution to fall detection using a simple graphical interface while not overwhelming the user with uncomfortable sensors.

Branch history guided instruction prefetching

Instruction cache misses stall the fetch stage of the processor pipeline and hence affect instruction supply to the processor. Instruction prefetching has been proposed as a mechanism to reduce instruction cache (I-cache) misses. However, a prefetch is effective only if accurate and initiated sufficiently early to cover the miss penalty. This paper presents a new hardware-based instruction prefetching mechanism, Branch History Guided Prefetching (BHGP), to improve the timeliness of instruction prefetches. BHGP correlates the execution of a branch instruction with I-cache misses and uses branch instructions to trigger prefetches of instructions that occur (N-1) branches later in the program execution, for a given N>1. Evaluations on commercial applications, windows-NT applications, and some CPU2000 applications show an average reduction of 66% in miss rate over all applications. BHGP improved the IPC bp 12 to 14% for the CPU2000 applications studied; on average 80% of the BHGP prefetches arrived in cache before their next use, even on a 4-wide issue machine with a 15 cycle L2 access penalty.

Improving the accuracy and performance of memory communication through renaming

As processors continue to exploit more instruction-level parallelism, a greater demand is placed on reducing the effects of memory access latency. In this paper, we introduce a novel modification of the processor pipeline called memory renaming. Memory renaming applies register access techniques to load instructions, reducing the effect of delays caused by the need to calculate effective addresses for the load and all preceding stores before the data can be fetched. Memory renaming allows the processor to speculatively fetch values when the producer of the data can be reliably determined without the need for an effective address. This work extends previous studies of data value and dependence speculation. When memory renaming is added to the processor pipeline, renaming can be applied to 30% to 50% of all memory references, translating to an overall improvement in execution time of up to 41%. Furthermore, this improvement is seen across all memory segments-including the heap segment, which has often been difficult to manage efficiently.

Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache

Very small instruction caches have been shown to greatly reduce fetch energy. However, for many applications the use of a small filter cache can lead to an unacceptable increase in execution time. In this paper, we propose the tagless hit instruction cache (TH-IC), a technique for completely eliminating the performance penalty associated with filter caches, as well as a further reduction in energy consumption due to not having to access the tag array on cache hits. Using a few metadata bits per line, we are able to more efficiently track the cache contents and guarantee when hits will occur in our small TH-IC. When a hit is not guaranteed, we can instead fetch directly from the L1 instruction cache, eliminating any additional cycles due to a TH-IC miss. Experimental results show that the overall processor energy consumption can be significantly reduced due to the faster application running time and the elimination of tag comparisons for most of the accesses.

iWander: An Android application for dementia patients

Non-pharmacological management of dementia puts a burden on those who are taking care of a patient that suffer from this chronic condition. Caregivers frequently need to assist their patients with activities of daily living. However, they are also encouraged to promote functional independence. With the use of a discrete monitoring device, functional independence is increased among dementia patients while decreasing the stress put on caregivers. This paper describes a tool which improves the quality of treatment for dementia patients using mobile applications. Our application, iWander, runs on several Android based devices with GPS and communication capabilities. This allows for caregivers to cost effectively monitor their patients remotely. The data uncollected from the device is evaluated using Bayesian network techniques which estimate the probability of wandering behavior. Upon evaluation several courses of action can be taken based on the situations severity, dynamic settings and probability. These actions include issuing audible prompts to the patient, offering directions to navigate them home, sending notifications to the caregiver containing the location of the patient, establishing a line of communication between the patient-caregiver and performing a party call between the caregiver-patient and patients local 911. As patients use this monitoring system more, it will better learn and identify normal behavioral patterns which increases the accuracy of the Bayesian network for all patients. Normal behavior classifications are also used to alert the caregiver or help patients navigate home if they begin to wander while driving allowing for functional independence.

Region-based caching: an energy-delay efficient memory architecture for embedded processors

Power consumption has been a major concern in designing microprocessors for portable systems such as notebook computers, hand-held computing and personal telecommunication devices. As these devices increase in popularity and are used in a wider range of applications, a low power design becomes more critical. In this paper, we propose a new microarchitectural data cache design called region-based caching that can reduce power consumption. Power savings is achieved by re-organizing the the rst level cache to more eÆciently exploit memory reference characteristics produced by programming language semantics. These characteristics enable the cache to be partitioned by memory region (stack, global, heap), reducing power consumption, while retaining comparable performance to a conventional cache design. Applications from the MediaBench benchmark suite indicate that a design with two additional small region-based caches results in 66% reduction in average in energy-delay product.

Utilizing reuse information in data cache management

1. ABSTRACT As microprocessor speeds continue to outgrow memory subsystem speeds, minimizing the average data access time grows in importance. As current data caches are often poorly and inefficiently managed, a good management technique can improve the average data access time. This paper presents a comparative evaluation of two approaches that utilize reuse information for more efficiently managing the firstlevel cache. While one approach is based on the effective address of the data being referenced, the other uses the program counter of the memory instruction generating the reference. Our evaluations show that using effective address reuse information performs better than using program counter reuse information. In addition, we show that the Victim cache performs best for multi-lateral caches with a direct-mapped main cache and high L2 cache latency, while the NTS (effective-addressbased) approach performs better as the L2 latency decreases or the associativity of the main cache increases.

Stack value file: custom microarchitecture for the stack

As processor performance increases, there is a corresponding increase in the demands on the memory system, including caches. Research papers have proposed partitioning the cache into instruction/data, temporal/non-temporal, and/or stack/non-stack regions. Each of these designs can improve performance by constructing two separate structures which can be probed in parallel while reducing contention. In this paper, we propose a new memory organization that partitions data references into stack and nonstack regions. Non-stack references are routed to a conventional cache. Stack references, on the other hand, are shown to have several characteristics that can be leveraged to improve performance using a less conventional storage organization. This paper enumerates those characteristics and proposes a new microarchitectural feature, the stack value file (SVF), which exploits them to improve instruction-level parallelism, reduce stack access latencies, reduce demand on the first-level cache, and reduce data bus traffic. Our results show that the SVF can improve execution performance by 29 to 65% while reducing overhead traffic for the stack region by many orders of magnitude over cache structures of the same size.

The effects of predicated execution on branch prediction

High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this problem as well, as they move towards deeper pipelines and support for multiple instruction issue. Branch prediction schemes are often used to alleviate the negative impact of branch operations by allowing the speculative execution of instructions after an unresolved branch. Another technique is to eliminate branch instructions altogether. Predication can remove forward branch instructions by translating the instructions following the branch into predicate form. This paper analyzes a variety of existing predication models for eliminating branch operations, and the effect that this elimination has on the branch prediction schemes in existing processors, including single issue architectures with simple prediction mechanisms, to the newer multi-issue designs with correspondingly more sophisticated branch predictors. The effect on branch prediction accuracy, branch penalty and basic block size is studied.

Practical exhaustive optimization phase order exploration and evaluation

Choosing the most appropriate optimization phase ordering has been a long-standing problem in compiler optimizations. Exhaustive evaluation of all possible orderings of optimization phases for each function is generally dismissed as infeasible for production-quality compilers targeting accepted benchmarks. In this article, we show that it is possible to exhaustively evaluate the optimization phase order space for each function in a reasonable amount of time for most of the functions in our benchmark suite. To achieve this goal, we used various techniques to significantly prune the optimization phase order search space so that it can be inexpensively enumerated in most cases and reduce the number of program simulations required to evaluate program performance for each distinct phase ordering. The techniques described are applicable to other compilers in which it is desirable to find the best phase ordering for most functions in a reasonable amount of time. We also describe some interesting properties of the optimization phase order space, which will prove useful for further studies of related problems in compilers.