Gaston Cambon

New nonvolatile FPGA concept using magnetic tunneling junction

This paper describes a real time reconfigurable (RTR) micro-FPGA using new non volatile memory. Magnetic tunneling junctions (MTJ) used in magnetic random access memories (MRAM) are compatible with classical CMOS processes. Moreover remanent property of such a memory could limit configuration time and power consumption required at each power up of the device. Each configuration memory point has to be readable independently from each other, which makes this approach radically different from the classical memory array one

Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications

New parallel execution based machine paradigms must be considered. Thanks to their high level of flexibility structurally programmable architectures are potentially interesting candidates to overcome classical CPUs limitations. Based on a parallel execution model, we present in this paper a new dynamically reconfigurable architecture, dedicated to data oriented applications acceleration. Principles, realizations and comparative results will be exposed for some classical applications, targeted on different architectures.

Metrics for reconfigurable architectures characterization: remanence and scalability

Target applications for mobile devices such as PDA and cellular telephones require increasingly powerful architectures. This challenge has spawned different hardware acceleration styles like configurable instruction set processors, coprocessors, and ASIC. Despite acceptable, these solutions show today a lack of flexibility considering rapidly changing standards. Structurally programmable architectures can today provide a trade-off between performance of hardwired logic and flexibility of processors. More and more reconfigurable architectures are today available as IP cores for SoC designers. These ones often differ according to several parameters (granularity, reconfiguration mode, topology...). Therefore, it is not straightforward to compare different architectures and choose the right one considering both actual and future requirements. This paper proposes a general model for reconfigurable architectures and gives a set of metrics which prove useful for architecture characterization. The methodology is illustrated on a dynamically reconfigurable architecture: the systolic ring.

Current mask generation: a transistor level security against DPA attacks

The physical implementation of cryptographic algorithms may leak to some attacker security information by the side channel data, as power consumption, timing, temperature or electromagnetic emanation. The differential power analysis (DPA) is a powerful side channel attack, based only on the power consumption information. There are some countermeasures proposed at algorithmic or architectural level that are expensive and/or complexes. This paper addresses the DPA attack problem by a novel and efficient transistor-level method based on a power consumption control, without any modification on the cryptographic algorithms, messages or keys

Magnetic tunnelling junction based FPGA

The aim of this paper is to propose a real time reconfigurable (RTR) micro-FPGA using new non volatile memory. Magnetic tunneling junctions (MTJ) used in Magnetic random access memories (MRAM) are compatible with classical CMOS processes. Moreover remanent property of such a memory could limit configuration time and power consumption required at each power up of the die. Nevertheless, each configuration memory point has to be readable independently from each other, that is why the approach is different from the classical memory array one.

A functional BIST approach for FIR digital filters

Presents a functional level built-in self-test of digital filters. This BIST technique is based on predetermined patterns which are not dependent on the filter implementation. Many examples show that stuck-at fault coverage is about 98%.<<ETX>>

Technological hybridization for efficient runtime reconfigurable FPGAs

The goal of this paper is to propose an FPGA using emerging non volatile technologies for its configuration memory. Studies on magnetic memories have already been carried out (Bruchon et al., 2006) but solid electrolyte and phase change memories are also good candidates for such type of application. Features of these technologies can provide some interesting characteristics to the FPGA such as short writing time with non volatile technology. A small structure (RSRAM) for remanent SRAM is used to convert information from these technologies into electrical information. This structure naturally provides some more features like partial and shadowed reconfiguration

A dynamically reconfigurable architecture for embedded systems

The Internet is becoming one of the key features of tomorrows communication world. The evolution of mobile telephone networks, such as UMTS, will soon allow everyone to be connected everywhere. These new network technologies bring the ability to deal not only with classical voice or text messages, but also with improved content, i.e. multimedia. At the mobile level, this kind of data-oriented content requires highly efficient architectures; and nowadays, embedded system-on-chip solutions are no longer able to manage critical constraints like area, power and data-computing efficiency. In this paper, we propose a new, dynamically reconfigurable network, dedicated to data-oriented applications such as, for instance, one targeted on third-generation networks. Principles, realisations and comparative results are exposed for some classical applications, targeted on different architectures.

The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems

Internet is becoming one of the key features of tomorrows communication world. The evolution of mobile phones networks, such as UMTS will soon allow everyone to be connected, everywhere. These new network technologies bring the ability to deal not only with classical voice or text messages, but also with improved content: multimedia. At the mobile level, this kind of data oriented content requires highly efficient architectures; and nowadays mobile system-on-chip solutions will no longer be able to manage the critical constraints like area, power and data computing efficiency. In this paper we will propose a new dynamically reconfigurable network, dedicated to data oriented applications such as the one allowed on third generation networks. Principles, realizations and comparative results will be exposed for some classical applications targeted on different architectures.

Dynamic hardware multiplexing: improving adaptability with a run time reconfiguration manager

Dynamic reconfiguration provides interesting features offering hardware flexibility and adaptability. Unfortunately, the lack of programming tools to manage it has limited its use in current SoCs. This paper presents a method to abstract, at design-time, dynamic reconfiguration management. Dynamic hardware multiplexing is a generic principle based on a scheduler dedicated to reconfigurable resources management at run-time. Formal background, implementation, simulation results and validations are exposed to illustrate the contribution of this study