Gaurav Saini

IMPACT OF RADIAL COMPRESSION ON THE CONDUCTANCE OF CARBON NANOTUBE FIELD EFFECT TRANSISTORS

The electronic behavior of semiconducting carbon nanotubes based CNTFET under the influence of radial deformation defect present in the channel is theoretically investigated using nonequilibrium Greens function method self-consistently coupled with three-dimensional electrostatics. It was found that deformation in the CNTFET channel composed of a small diameter semiconducting carbon nanotube can increase its conductance by a factor of 4 or more depending upon the average reduction in the C–C bond length after compression. This increase in CNTFET conductance is directly related to the movement of the electronic states toward the Fermi level when the tubes are squeezed. Furthermore, the device ON–OFF current ratio also decreases with increase in applied compression which makes it hard to switch-OFF the device.

Low power high throughput current mode signalling technique for global VLSI interconnect

This paper investigates a low power, high speed & energy efficient current mode signaling technique. For current mode (CM) signaling a complete system consists of driver & receiver with decoding circuit. By analytical analysis it is also proved that the current mode signaling technique offer a three times improvement in performance parameter i.e. delays when compared to voltage mode. A new low swing current mode interconnect system is proposed, whose performance is further improved by reducing the input impedance of current mode system. The proposed low swing current mode interconnect system gives 66.46% and 60.66% improvement in delay when compared with voltage mode (VM) and VM with repeater insertion. Also reduced input impedance CM system offers 87.03% and 84%, reduction in delay when compared with the conventional voltage mode and voltage mode with repeater inserted signaling technique. Proposed low swing CM model consume 11% less power for data rate of 4Gbps. Similarly, CM dissipates 0.05pJ energy whereas VM consume 0.106pJ for a single bit transmission across the interconnect.

Leakage behavior of underlap FinFET structure: A simulation study

Bulk MOSFET is reaching to its physical limit with the advancement of technology. The key factor which influences the performance of bulk MOSFET in nano regime is the gate oxide thickness. In this work an attempt has been made to analyze the underlap FinFET structure using 2D simulation. ITRS 2009 high performance (HP) updates for the year of 2015 is used in this work. Study of n-type underlap FinFET structure is carried out to analyze the effects of metal gate with high-k dielectric. Use of high-k dielectrics with metal gate at a given EOT can improve the gate leakage current without harming the device performance. Underlap structure provides an improvement in the off-state leakage current than the overlap structure. Effects of gate workfuction variation on the performance of underlap FinFET structure is also studied in this paper.

A stable and power efficient SRAM cell

In this paper, we designed a 9T SRAM cell using dual voltage threshold (DVT) and stacking effect. To achieve high density, low power and high performance, device scaling has been continuously done that result in increase in leakage power dissipation. At sub-micron technology, about 30% of total power dissipation is due to leakage power dissipation. The purpose of this paper is to analyze the Performance parameters like SNM (static noise margin) in all modes of operations, leakage power dissipation, writes and read access delay. In this paper, we analyzed the comparative parameters in 6T, 7T and proposed 9T SRAM Cell. The proposed 9T SRAM Cell gives improved SNM and reduced leakage power at the cost of small area overhead. The circuit was implemented using cadence Virtuoso tools in 180-nm technology.

Stacked keeper with body bias: A new approach to reduce leakage power for low power VLSI design

In this paper we present a technique named as stacked keeper with body bias (SK-BB). It uses stack effect to existing sleepy keeper technique along with body bias for ultra low static power consumption. A 4-bit CMOS adder circuit is designed using existing techniques like sleep, zig-zag, sleepy-stack, dual stack, sleepy-keeper and proposed techniques SK-BB and SK-BB with High Vth (SK-BBH). Simulation study shows SK-BB and SK-BBH achieves lowest static power consumption among all above techniques. SK-BB and SK-BBH achieves 53% and 34% of less static power than sleepy keeper approach. The dynamic power of SK-BB and SK-BBH are 1% more and 9% less than sleepy keeper approach. However, the delay of the SK-BB and SK-BBH increases by 59% and 4% than sleepy keeper.

Design of a novel regulated cascode current mirror

In this paper, a novel regulated cascode current mirror is proposed. In proposed structure cascode stage is used to enhance the output impedance of existing regulated cascode current mirror. A feedback loop is used to stabilize the output current. Output impedance of proposed circuit is three times improved and power dissipation is same as existing regulated cascode current mirror at the cost of high systematic gain error. The output current is mirrored with a transfer error less than 1% when the input current is increased from Zero to Twenty micro ampere thats why the proposed circuit can be used for low power application.

Heterojunction tunnel FET with Heterodielectric BOX

In this paper, a Heterojunction Tunnel FET is reported which has a two stage reduction in ambipolar current. To obtain high ON-state conduction current, a lower band gap material at the source side and high-k spacers are used. From the simulations studies, ON-state conduction current is found to be 0.19 mA/μm at a tunneling width of 2.47 nm. Moreover, ON-state conduction current is enhanced to 0.58 mA/μm. The effect of spacer length on ambipolar current is also reported. In this brief, we used Heterodielectric BOX (HDB) to reduce ambipolar current.

Enhanced cascode node impedance to the improved recyclic folded cascode OTA

This paper presents improved recyclic folded cascode OTA (IRFC) with enhanced cascode node impedance. It is the improved version of the conventional improved recyclic folded cascode OTA with enhanced gain parameter. The concept of positive feedback is used to increase the impedance of cascode node in existing IRFC technique. Proposed technique has a higher gain with small change in bandwidth and same power consumption. The proposed scheme is simulated at 180nm technology node with all the transistors operating in saturation region. It is found that there is increment in gain from 52dB to 61dB without changing unity gain bandwidth (UGB).