Geetani Edirisooriya

Design of low cost ROM based test generators

A data compression technique for ROM based built-in test generators of combinational circuits is described. Some of the test pattern bits are computed using the reduced data stored in the ROM combined with the address bits accessing the ROM. Some experimental results are presented for ISCAS benchmark circuits and random data.<<ETX>>

Cyclic code weight spectra and BIST aliasing

In built-in self-test for logic circuits, test data reduction can be achieved using a linear feedback shift register. The probability that this data reduction will allow a faulty circuit to be declared good is the probability of aliasing. Based on the independent bit-error model, we show that the code spectra for the cyclic code generated by the feedback polynomial can be used to obtain an exact expression for the aliasing probability of a multiple input signature register when the test length is a multiple of the cycle length. Several cases are examined and, as expected, primitive feedback polynomials provide the best performance. Some suggestions to avoid peaks in the aliasing probability are given.

Aliasing probability in multiple input linear signature automata for q-ary symmetric errors

The aliasing probability in single and multiple input linear automata signature registers (LASRs: linear feedback shift registers (LFSRs) and linear cellular automata) has been widely studied under the independent bit error model. Aliasing in a class of multiple-input LASRs (MILASRs) under the q-ary symmetric error model is examined. By modeling the signature analyzer as a two state Markov process, it is shown that the closed form expression previously derived for aliasing probability for multiple-input LFSRs with primitive polynomials holds for a far more general class of linear automata signature analyzers, including all multiple-input LFSRs. An easily verifiable criterion is given to determine whether a MILASR falls into this category. It is shown that for q-ary symmetric errors, the circuit complexity and the propagation delay can be minimized by using a set of m single bit LFSRs.<<ETX>>

Enhancing vector access performance in CRAY X-MP memory system

The authors propose a simple modification to the conflict resolution scheme that will significantly improve the performance of the CRAY X-MP memory system. In particular, they show that it is possible to avoid linked conflicts due to a single CPU altogether by changing the priorities of active vector streams when a memory port encounters a memory bank conflict. Some examples are presented to show how the proposed scheme prevents these linked conflicts.<<ETX>>

Minimizing testing time in scan-path architecture

In general test pattern generators attempt to generate a minimum number of test vectors to detect all or most detectable faults for a given fault model. It is implicitly assumed that the individual test vectors of the test set are applied in parallel. In the boundary scan technique the test vectors are typically shifted serially to the scan register to stimulate the logic circuit. Therefore, O(nT) clock cycles are needed to apply the test set serially, where n is the number of inputs of the logic circuit and T is the number of test vectors in the test set. The authors present a heuristic algorithm to reduce the length of the bit sequence that is shifted serially to generate a given test set. They show the results obtained for randomly generated test sets. The percentage reduction in testing time is computed.<<ETX>>

Aliasing in multiple-valued test data compaction

The possibility of using multivalued instead of binary linear multiple input shift registers (MISRs) for output compaction of multiple-valued logic circuits is discussed. The use of multivalued MISRs avoids the need for decoding the signals. A framework for examining aliasing in multiple-valued circular MISRs is presented. The exact aliasing probability is obtained for ternary and quaternary MISRs under an independent error model for an arbitrary test length. It is shown that multivalued MISRs perform better than their binary counterparts.<<ETX>>

Distributing load in the presence of failures in extra-stage shuffle-exchange networks

Multipath multistage interconnection networks (MINs) have been proposed to increase reliability in shared memory multiprocessor systems. The authors address the problem of evenly distributing traffic among surviving switching elements in the presence of switch failures. They consider the 16*16 extra stage cube (ESC) network. A simple modification to the ESC network is outlined. Hardware cost is not increased as the modified network uses the same number of links as the ESC network. Like the ESC network the proposed MIN tolerates all single component failures. In addition, it is shown that the proposed MIN tolerates multiple switch failures better than the ESC network.<<ETX>>

Closed form aliasing probability for Q-ary symmetric errors

In built-in self-test schemes multiple-input signature registers (MISRs) are often used to compact test data. The error escape probability during compaction determines the quality of the compactor. The authors derive closed-form expressions for exact aliasing probability under the Q-ary error model for a large class of MISRs. It is shown that for Q-ary symmetric errors, the circuit complexity and propagation delay can be minimized by using a set of m single-bit linear feedback shift registers without increasing the aliasing probability. This also leads to a regular register structure.<<ETX>>

A class of correlated traffic models for measuring multiprocessor performance

A new class of traffic models is proposed to evaluate performance in shared memory multiprocessors. In contrast to previous traffic models, the proposed models do not assume the mutual independence of requests generated by processors in a given memory cycle. Expressions are derived to compute bandwidth in bus networks. Also, some numerical results are provided for bus networks. These results are useful when designing multiple bus multiprocessors.<<ETX>>

A signature efficient solution for remote file comparison

In distributed systems files are replicated to enhance availability and reliability. The authors provide an algorithm based on coding theory to significantly reduce the number of signatures needed to precisely diagnose differing pages in remotely located file copies. The method needs only one message transmission. A unique feature of this method is the ability to precisely diagnose up to t differing pages with just 2t signatures, independent of the files size. The maximum number of pages in a file is determined only by the number of bits in a signature. If a signature has m bits, the proposed technique can precisely identify t(t<2/sup m-1/ page differences in a file that has up to 2/sup m/-1 pages.<<ETX>>