Gehad I. Alkady

A fault-tolerant technique to detect and recover from open faults in FPGA interconnects

Nowadays, FPGAs play a great role in electronic circuits design especially in implementing critical applications. As a result, the need for adding fault-tolerance to FPGAs becomes very important. In this paper, a fault-tolerant technique and associated modifications on FPGA architecture are proposed. This technique can detect and recover from open faults in programmable interconnects. It was successfully simulated using an FPGA-based simulator.

Integration of Multiple Fault-Tolerant techniques for FPGA-based NCS Nodes

Fault-Tolerance is quickly becoming a very important issue in the design of industrial automation systems. This paper addresses this issue in the context of temporary failures occurring in harsh industrial environments. The Fault-Tolerant design of sensors and controllers is investigated for both the In-Loop and Sensor-to-Actuator architectures. Processing is implemented on FPGAs whenever possible. Triple Modular Redundancy (TMR) is used to implement sensors for fast varying applications while Temporal Redundancy (TR) is used for sensors for slow varying applications in order to reduce cost without affecting system reliability. Dynamic Partial Reconfiguration (DPR) is used for fault recovery. Reliability models are developed for all Fault-Tolerant blocks to help system designers with the choice of the Fault-Tolerant techniques to be implemented. Two case studies are carried out with different numbers of fast and slow sensors. System reliabilities are calculated for both conventional and hybrid NCS systems. Results show that the proposed technique results in a cost-effective system at the expense of a very slight decrease in reliability.

Dynamic fault recovery using partial reconfiguration for highly reliable FPGAs

FPGAs are becoming more popular in the domain of safety-critical applications (such as space applications) due to their high performance, re-programmability and reduced development cost. Such systems require FPGAs with self-detection and self-repairing capabilities in order to cope with errors due to the harsh conditions that usually exist in such environments. In this paper, a new dynamic fault recovery technique is proposed using the runtime partial reconfiguration (PR) property in FPGAs. It focuses on open interconnect faults and relies on specifying a Partially Reconfigurable block in the FPGA that is only used during the recovery process after the failure of the first module in the system. The technique uses only one location to recover from errors in any of the FPGAs modules. Accordingly, it requires less area overhead when compared to other techniques.

FPGA-based reliable TMR controller design for S2A architectures

Fault-tolerance is becoming an essential feature in the design of Networked Control Systems (NCSs). Furthermore, Sensor-to-Actuator (S2A) architectures have shown some advantages over conventional In-Loop architectures. This paper focuses on fault-tolerant controllers in the context of S2A systems. It proposes the use of Triple Modular Redundancy at the controller level. The fault-tolerant controller will be hosted in an FPGA that has a spare location. The voter in this TMR scheme is fault-secure to guarantee that the controllers never produce an undetected incorrect control action. Finally, system reliability is calculated using Markov models to quantitatively show, via case studies, the advantage of the proposed technique in terms of extended lifetime.

Fault-Tolerant FPGA-based controllers in factory automation

Nowadays, FPGA-based Networked Control Systems (NCSs) are frequently used. Transient and permanent faults occur often as a result of radiation in industrial environments. Accordingly, Fault-Tolerant (FT) FPGA-based NCSs are desired. In this paper, an NCS model is proposed composing of In-Loop and S2A architectures linked via an Ethernet switch. This architecture is used in shape detection machines with vision sensing requirements. FT techniques are applied in the controller nodes of the system along with Dynamic Partial Reconfiguration (DPR) for FPGA-based controller recovery. The reliability of the system due to changes in both the recovery rate and the conditional probability of failure occurrence (either transient or permanent), is presented in this paper. Accordingly, a Markov model is constructed for reliability calculations. A case study is used to illustrate the use of such a model to choose appropriate maintenance strategies as well as a quantitative measure for the ability of the FT techniques to increase system reliability.

FPGA-based reliable video sensor in NC

Recently, FPGA-based NCS applications have been widely used. Industrial environments have a lot of electromagnetic interference which may induce transient and permanent faults. As a result, Fault-Tolerant FPGA based NCS applications are required. In this paper, an NCS model composed of a combination of S2A architecture and In-Loop architecture connected to each other through Ethernet switch, is described. The S2A part of the model is an FPGA-based video sensor network which requires protection against transient faults. Several Fault-Tolerant techniques are mentioned in the literature for protection. Two Fault-Tolerant techniques are under study which are Hot Standby and Sift-Out. The fault model used is Single Event Upsets (SEUs). Dynamic Partial Recovery is used. Markov Models are used for reliability calculations. Results show that even though the Sift-Out technique is more reliable than Hot Standby, there may be situations where the difference in reliability cannot justify the extra cost.

Using power consumption in the performability of Fault-Tolerant FPGAs

Over the last decade, several Fault-Tolerant techniques for FPGAs were proposed especially for recovering from permanent faults. Most of those techniques were based on relocation of the defective module into a new location acting as a spare. Accordingly, what is the suitable number of spares that should be added to a system? In this paper, a performability model is developed to quantitatively investigate the appropriate number of spares The model uses power consumption as the penalty. An example with three Markov models is studied to show system designers how to find the appropriate tradeoff between increase in reliability and decrease in performability.