Geng Li

A 0.6-V 8.3-ENOB asynchronous SAR ADC for biomedical applications

A microwatt asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented. The supply voltage of the SAR ADC is decreased to 0.6 V to fit the low voltage and low power requirements of biomedical systems. The tail capacitor of the DAC array is reused for least significant bit conversion to decrease the total DAC capacitance thus reducing the power. Asynchronous control logic avoids the high frequency clock generator and further reduces the power consumption. The prototype ADC is fabricated with a standard 0.18 μm CMOS technology. Experimental results show that it achieves an ENOB of 8.3 bit at a 300-kS/s sampling rate. Very low power consumption of 3.04 μW is achieved, resulting in a figure of merit of 32 fJ/conv.-step.

A novel buck/LDO dual-mode DC—DC converter for efficiency improvement

A novel buck/LDO dual-mode (BLDM) converter using a multiplexing power MOS transistor is proposed, which adaptively switches between buck mode and LDO mode to improve conversion efficiency. The chip was fabricated in a standard 0.35 μm CMOS process. Measurement results show that the peak efficiency is 97%. For the light load operation, the efficiency is improved by 14%. The efficiency keeps higher than 82.5% for the load current of 50 mA without any complex control or extra EMI due to the normal method of pulse frequency modulation (PFM) control used for improving the light load efficiency. It does not cost much extra chip area because no additional regulator PMOS is needed. It is more suitable for noise-restricted systems and battery-powered electronic devices for when battery voltage drops because of long hours of work.