Georg Denk

Transient Noise Simulation: Modeling and Simulation of 1/f -Noise

In this paper we present a new approach for the transient noise simulation of electronic circuits with stochastic differential algebraic equations (SDAEs). The first part treats the modeling of noise in the time domain which is accomplished with generalized stochastic processes. This allows not only to model white noise like thermal and shot noise, but also 1/f-noise or flicker noise. It is shown that fractional Brownian motion reflects the properties of 1/f -noise, namely a spectrum proportional to 1/f with f denoting the frequency. Some consequences of this approach on the solvability of the circuit equations are presented. In the second part we give remarks on the implementation of numerical schemes for SDAEs. Besides the integration scheme itself the generation of appropriate random numbers is a major issue. Finally we present some numerical experiments.

Modelling and simulation of transient noise in circuit simulation

Abstract This paper presents a new approach to the transient noise analysis of integrated circuits. This approach consists of two parts, the modelling of noise sources in the time domain and the development of numerical schemes for stochastic differential-algebraic equations. The noise sources include thermal noise, shot noise, and flicker noise and their modelling is based on generalized stochastic processes. Brownian motion is the starting point for the modelling of white-noise sources (thermal and shot noise), while fractional Brownian motion is used for flicker noise sources. The numerical schemes employed for the computation of solution paths adapt well-known methods for stochastic differential equations to the specific situation within circuit simulation. Under the assumption of small noise the convergence properties of the drift-implicit Euler scheme and the drift-implicit Milstein scheme are proved. Finally numerical experiments with real-world circuits are presented.

Efficient transient noise analysis in circuit simulation

Transient noise analysis means time domain simulation of noisy electronic circuits. We consider mathematical models where the noise is taken into account by means of sources of Gaussian white noise that are added to the deterministic network equations, leading to systems of stochastic differential algebraic equations (SDAEs). A crucial property of the arising SDAEs is the large number of small noise sources that are included. As efficient means of their integration we discuss adaptive linear multi-step methods, in particular stochastic analogues of the trapezoidal rule and the two-step backward differentiation formula, together with a new step-size control strategy. Test results including real-life problems illustrate the performance of the presented methods.

A Demonstrator Platform for Coupled Multiscale Simulation

In this communication we present the CoMSON Demonstrator Platform (DP), a software tool designed to help researchers in testing and validating models and algorithms for coupled simulation of nanoelectronic circuits and devices. The structure of the DP is presented with an explanation of the motivations behind the critical design choices. A multilevel simulation of a CMOS AND gate using two different coupling algorithms is provided as an application example. The example is intended to demonstrate the suitability of the DP as a flexible prototyping environment and its ability to cope with real life industrial problems. In the numerical simulations both the semi-classical Drift-Diffusion model (DD) and a Quantum Corrected DD model (QCDD) are employed and their predictions are compared.

Modelling and simulating charge sensitive mos circuits

We show how charge distribution effects in MOS transistors are reflected only correctly by models based on the physical properties of the device. Hence one has to consider carefully the impact of modelling to obtain correct results for MOS circuits by numerical simulation. Additionally, the choice of an appropriate integration scheme is essential for both reliable and efficient simulation results. To spotlight these influences, we use a charge pump as an instructive test circuit and discuss a variety of modelling approaches.

Automatic Thermal Network Extraction and Multiscale Electro-Thermal Simulation

We present a new strategy to perform chip-level electro-thermal simulation. In our approach electrical behaviour of each circuit element is modeled by standard compact models with an added temperature node (1; 2). Mutual heating is accounted for by a 2-D or 3-D diffusion reaction PDE, which is coupled to the electrical network by enforcing instantaneous energy conservation. To cope with the multiscale nature of heat diffusion in VLSI circuit a suitable spatial discretization scheme is adopted which allows for efficient meshing of large domains with details at a much smaller scale. Preliminary numerical results on a realistic test case are included as a validation of the model and of the numerical method.

A holistic fast and parallel approach for accurate transient simulations of analog circuits

The accurate analog simulation of critical circuit parts is a key task in the R&D process of integrated circuits. With the increasing complexity of integrated circuits it is becoming cumulatively challenging to simulate in the analog domain and within reasonable simulation time. Previous speedup approaches of the SPICE (Simulation Program with Integrated Circuit Emphasis) analog circuit simulator included either solver improvements and speedup or model order reduction of the semiconductor devices.In this paper we present a comprehensive approach to significantly speedup a SPICE-based analog circuit simulator while keeping the single-rate characteristic of time domain simulations. The novelty of our approach consists in the combination and extension of existing approaches in a unique way, enabling fast transient SPICE-level simulations. The main component of our approach is the circuit partitioner that combines relevant aspects from circuit theory and linear algebra in a unifying way. This enables the construction of an efficient and parallel BBD (bordered block diagonal) solver. Furthermore, this BBD structure allows for intrinsic model order reduction of the partitions during the Newton iteration, transforming the Newton method to a Quasi-Newton method.For mid-sized and large-sized circuits our BBD approach leads to significant sequential and parallel accelerations of transient simulations. Additional speedup can be gained from our block-bypass strategies exploiting the latency in the partitioned circuit. Altogether our approach leads to a speedup of up to two orders of magnitude compared to the state-of-the-art KLU solver while maintaining SPICE-level accuracy.

COMSON Demonstrator Platform

This chapter describes the Demonstrator Platform (DP), a framework for simulation of devices, interconnects, circuits, electromagnetic fields, and thermal effects. This framework is used to develop and test new mathematical methods and algorithms. Section 8.1 describes the design of the DP and gives an overview of the available modules. Section 8.2 is a tutorial on how to use the DP focusing on model-order reduction. It shows for the example of a micro-hotplate model all the steps needed to apply model-order reduction, including postprocessing and error estimation. In a second part, a coupled simulation of a circuit combined with a reduced model of a transmission line is presented. Section 8.3 emphasizes the aspect of the DP as a development framework. After introducing the benchmark example of an n-channel power MOS-FET, it is shown how to combine and extend different modules of the DP to a fully coupled electro-thermal simulation of the device.