George Chen

A software-based real-time MPEG-2 video encoder

Dedicated hardware previously has been required to perform real-time MPEG-2 video encoding. However, with increases in clock frequency and the introduction of video-specific instruction sets, general-purpose processors can now approximate the function and performance of single-function hardware. In this paper, we describe a software-only MPEG-2 (MP@ML) video encoder implemented on a personal computer using an Intel/sup TM/ Pentium(R) III processor. This encoder is capable of real-time operation while consuming less than 70% of the processor. The main contribution of this work is a set of algorithmic simplifications that significantly reduces the computational load of the encoding process while only slightly degrading the subjective video quality compared to encoders that are more exhaustive.

3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration

A Field Programmable Gate Array (FPGA) family was designed to match a programmable fabric die built in 14nm process technology with 28Gb/s transceiver dice. The 2.5D packaging (Fig. 3.3.1) uses embedded interconnect bridges (EMIB) [1]. 20nm transceivers were reused enabling a transceiver roadmap independent of FPGA fabric. Fig. 3.3.2 shows a 560mm2 fabric die and six transceiver dice. The programmable fabric contains 2.8M logic elements, DSP, memory components, and routing interconnect operating at up to 1GHz. Applications drove the need for improved flexibility and security of the FPGA configuration system. A triple-modular redundant microprocessor-based secure device manager (SDM) was designed and is programmed by embedded software.